found these today
https://translate.google.com/translate?hl=el& … D18511%26st%3D0

https://www.ebay.com/itm/ABIT-386DX-FA3-Mainb … ordt=true&rt=nc

could they be of help?
I'm thinking that I have another 386x board so I might try to desolder the 386 in this board and if it fails I have the other one to live with. 🤣

I will steal a little the topic for a little 😀 to comment on the 386DX disable pin feipoa revealed to us... ofcourse on my mobo it had to be in a hard to reach place , right next to the FPU socket. 🤣
That's why I decided to ground it on a nearby capacitor's GND connection rather than the pin next to #FLT , it will be easier to revert the mod in the future if needed since the working space between the cpu and the fpu socket is ~4.5mm 😵

you can see the PGA132 space above the cpu - will solder it next and report back 😀

edit:
all fine

the onboard 386 still gets hot , I think I'll desolder it completely once I get a PGA version

Nice work. Did you check to see if FLT# is connected to anything? I don't see any top layer trace connected to it. So if it was left unconnected, you probably don't need to desolder the pin and lift it up.

FLT# was connected to a pad with a trace that went under the CPU, I could not investigate further as the tight space did not help...

Interesting. I wonder if the trace went to a jumper header or a solder pad somewhere? Did you measure if FLT# was connected directly to Vcc, or perhaps to a resistor to Vcc? What is the resistance between FLT# and Vcc?

it certainly does not connect directly to vcc or via a resistor.
I cannot measure - there is no space to work...!

Not even enough space to stick a wire or probe on the FLT# pin and measure the resistance to Vcc? It probably has a 2, 5, or 10K pull-up resistor.

see above , there is no resistance between the pad and 5v
maybe it goes nowhere, maybe connecting it directly to GND without lifting would work fine but I was feeling so adventurous 🤣

keropi wrote:

it certainly does not connect directly to vcc or via a resistor.

Sorry, looks like I glanced over the "or via a resistor" part.

^ yeah I added that later because I did measure when the pin was connected: no resistance between any voltage on the PSU plug

Well that is good to know. I was starting to wonder if I was having adverse symptoms of old age.

I managed to destroy the board 😁
now i wait for a hybrid 386/486 vl bus motherboard from ebay. Its model is 4D50L. it comes with a 486sx 33mhz, but i think I'll use the 486dlc 40 + iit 4c87dlc 40 combination. will i lose a lot of performance?

Could you describe in detail the horror you submitted to the motherboard?

you must like horror movies!! i just got rid of the 386dx cpu by cutting all its pins.... now the motherboard won't post and will definitely won't make any beep sound.... the 486dlc gets a bit warm but that's all... 🙁 it might be that some of those hardwired pins are preventing the dlc from being detected or that i did something horribly wrong.

you didn't want to just cut one pin (FLT#) and wire it to GND?

It seemed difficult at the time 🙁

Hi everyone 😀 ! It has been almost 3 years since the last post in this thread. I have a similar problem and therefore I thought I should rather post it here than in a new thread.
My mainboard is a "Unichip 367C Rev 1.0" or "UNI-386WB". The following picture is from amoretro.de:

My board is the same model and revision. It has an Am386DX-40 Revision D -PQFP-CPU. My board also came without the PGA 132 socket. I soldered in a PGA 132 socket. This is my board, PGA132 soldered in, 486DLC plugged in:

Without the 486DLC in the PGA 132 socket the board detects the 386DX CPU:

The 386DX gets mildy warm and everything seems stable.

When I plug in the 486DLC the board detects a 486SX CPU (see screenshot):

Now this is where the problems start: with the 486DLX plugged in, the board only boots sometimes. It takes a couple of tries (power on/ off).
In any case (whether it boots or not): The 386DX gets dangerously hot within seconds.

I did a quick measurement this morning. With the 486DLC plugged in I measured the 386DX FLT pin and it seems to be connected to GND (0 Ohms to mainboard power connector GND, mainboard off, AT- power-connector disconnected). I will repeat this tonight with more time, just to make sure that I didn't accidentally hit the adjacent GND-Pin. These tiny PQFP-Pins are hard to count with my vision 😉.

Keropi reported that his 386PQFP-CPU still got hot after the FLT-pin-mod.

So what should I do now? I dont really want to remove the 386DX entirely since Balthazor4ever destroyed his board that way.
Any ideas? At first I should probably repeat the measurement on pin 54 (FLT).

Unless your mobo is somehow different than mine, the FLT on the PQFP 386DX is not connected to anything. I certainly do not have any "automatic" disabling with the PGA CPU installed - and frankly, how would that even work, there is no special signal for that on 132-pin PGA (unlike on the 486 PGA, to disable the on-board SX).

I had to do a mod, see that missing DIP14 space for different clock generator? There is a jumper, not populated, next to the two existing ones that set CPU clock frequency. It connects to the missing chip only so you can put a third jumper there, and wire one end to the FLT pin. The other end is already GND I think (can't remember now), if not then just make that connection too. Floated 386 still uses some power but not much, the reason it gets hot is being so close to the DLC which itself runs hot. Slap a small, quiet fan on the DLC and it will solve both of these issues (especially for 40MHz operation).

Surprisingly the DLC is usually able to over-power the PQFP 386DX and it kinda works even without the FLT being properly grounded but as you can see, only kinda. It will not be stable, not to mention bad for both CPU fighting.

One more thing, the only correct DLC cache setup that works in BIOS is to set A20 mask to enabled and flushing to BARB. A20M is connected, sort of, it's provided by the keyboard controller (and that's all it used for it seems, the actual gating is done inside chipset) so do not enable fast A20 gate option. If you set A20 mask to disabled BIOS will configure the CPU to not cache first 64k of each 1MB region, that's perfomance loss and the mask signal is connected after all. Nothing else is though so BARB is the only option (do remember to set RAM refresh to hidden). While it might seem like FLUSH works too, it's only because most of the time the small L1 is evicted before it has a chance to cause collision. But it can randomly corrupt CPU state. Well, if you are going to do FLT mod then you can also add hardware for FLUSH too - I plan on doing that.

I measuered again and yes, pin 54 (FLT) is not connected to GND directly. I must have accidentally hit the adjacent pin 55. I used a much finer probe this time.

So thank you Deunan. You saved my day again. 😀

And yes, you are also right, one pin of that (missing) jumper you mentioned (JP76) is already connected to GND.

I did a quick test. I connected pin 54(FLT) with pin 55 on the 386DX without disconnecting pin 54 from its pad. I simply put a small piece of copper wire between the pins and voilà:

This time the board didn't detect a 486SX. It detected a Cx486DLC. Interesting.

Also, with the wire between pin 54 and 55 installed the 386DX doesn't get violenly hot anymore. It still gets warm but reasonably warm.

I think I will make that unused jumper (JP76) into an FLT ebable/disable jumper just as you suggested.... EDIT: Or maybe I am lazy and I will simply solder pin 54 and 55 together without disconnecting pin 54 from its pad. Thank you very much. I apply the suggested (bios) settings once the mod is done. 😀

OK. I modded the board as suggested by Deunan:

I installed a jumper for JP76. I connected the 386DX's pin 54 (FLT) to Pin 4 of the (missing) U99-IC. (The U99 CLK-generator-IC is missing in my board. It uses the CLK-generator in U35 instead.) Pin 4 of U99 has a trace to JP76. The other Pin of JP76 is connected to GND. JP76 is now te enable/disable-jumper for the 386DX.

@Deunan: You wrote that"...the only correct DLC cache setup that works in BIOS is to set A20 mask to enabled and flushing to BARB." By "set A20 mask to enabled" do you mean that I shoud set the Bios option "Cyrix A20M Pin" to enabled? :