Your Cyrix support in bios is way more sophisticated than mine. The only option I have is internal cache enable. It never really worked correctly so I use the software utility instead.

Anonymous Coward wrote on 2021-06-07, 10:59:

Your Cyrix support in bios is way more sophisticated than mine. The only option I have is internal cache enable. It never really worked correctly so I use the software utility instead.

Same. Mine just has a "486 Internal cache enable/disable" when the DLC is detected. It disappears when I have a 386DX installed.

alexthekid wrote on 2021-06-07, 10:05:

@Deunan: You wrote that"...the only correct DLC cache setup that works in BIOS is to set A20 mask to enabled and flushing to BARB." By "set A20 mask to enabled" do you mean that I shoud set the Bios option "Cyrix A20M Pin" to enabled? :

Make these changes (from my 40MHz DLC):
Slow Refresh -> OFF (ON might not be stable, you get next to nothing for turning it on anyway)
DRAM Read/Write -> try 1 WS (works for me, 8x 60ns sticks)
SRAM Write -> try 0WS (works for me, but I did eventually swap the 20ns chips for 15ns ones)
Cyrix settings are OK, that's the only working combo for this mobo without further mods.

DO NOT set the AT BUS Clock (aka ISA) to 7.xx MHz option, that is not functional. Not that you'd want to make it slower than 8MHz. You can overclock ISA by using smaller dividers, keep in mind this refers to CLK2 signal which is twice the CPU rated frequency. So /10 means 80/10=8MHz.

You might get some small performance uplift by disabling Local Ready Synchronized (it's supposed to be on for 40MHz according to various manuals) - frankly I see no difference either way.
Make sure you have Fast A20 Gate disabled in previous BIOS tab, and cache is set to Both (sometimes it glitches and sets just the internal or external when CPUs are swapped).

BTW 8 RAM sticks should be better than 4 due to banking, not as much as on ALI mobos but still. This mobo can only cache up to 16MB so don't put more, and I'm not sure if bank interleaving will be enabled for 16+4 setup, so I stick to 8MB total. If you need more than 8 you want a 486 system with 72-pin SIMMs or better anyway.

Thank you Deunan. :-)With your suggested settings the CPUs L1-Cache is enabled in write through mode (that is what the cyrix diagnosis software tells me).
Is it possible to set it to WB-mode?

Are there any other settings necessary beyond the bios settings? Do I have to use the cyrix.exe as on my other 386 motheroard, for example to define non-cachable regions?

alexthekid wrote on 2021-06-12, 10:33:

Thank you Deunan. :-)With your suggested settings the CPUs L1-Cache is enabled in write through mode (that is what the cyrix diagnosis software tells me).
Is it possible to set it to WB-mode?

Are there any other settings necessary beyond the bios settings? Do I have to use the cyrix.exe as on my other 386 motheroard, for example to define non-cachable regions?

No need to run any extra software, the BIOS is at least smart enough to set the two necessary exclusion zones for you, and so long you pick the right settings (BARB or FLUSH with HW mod) it'll work correctly.
These CPUs do not have the capability to use their cache in WB mode, only in WT. This mobo does WB (if you enable it) for L2 though, it's performance improvement but not huge.

Hi, I have previously mentioned 386 MB KMC-A419-8 with soldered onboard CPU Am386DX rev. D and now I sucessfully made a FLT# mod.
I sucked out the solder from PGA footprint and soldered on the PGA socket. Then I soldered a 2-pin jumper, one pin fitted into GND pin of unpopulated U21 footprint and second pin is connected to FLT# via fine wire. I measured that FLT# has internal pull-up to 5V cca 100k so I didn't added external PUP as the connection is quite short. This let me enable or disable onboard CPU on demand. So I tried 486DLC inside as BIOS supports it. I also added more cache up to 256kB (added 4x32kB chips and replaced 8kB tag by 32kB tag, jumpers had to be set by error-trial like this: JP5: 1-2, JP6: on, on, on). I tested in CCT386 and is seems 486DLC got less points on L2 cache performance over 386DX probably due to added overhead of L1-L2 pipeline...

Have you tried playing with the L1 cache using the Cyrix.exe tool?

https://www.philscomputerlab.com/cyrix-486dlc.html

I found that I needed to use it to get the best performance, even though the BIOS knew about the Cyrix chip.

Re: 486DLC cache coherency blues and headaches

No, I didn't. BIOS have L1 and L2 enable/diable options. Also CCT386 should enable and disable L1 via commandline option but it didn't have effect.