Lack of LDRQ means that DMA controller should be finally deleted from the chipset, which means it should be possible to create your own over PCI or PCI-E and no longer need LPC for anything except for SERIRQ signal. FPGA will be necessary though, CPLD will be too small for such a stunt. PCI-E puts big latency on IO operations and the result may be fairly wonky, it is all untreaded territory and not something I'll venture into anytime soon.
EDIT: I have been looking at how IRQs work for PCI-E and you cannot actually target any specific IRQ with it. There's two mechanisms : the legacy INTA/B/C/D mechanism of normal PCI and "message signaled interrupts" and those can only be used with APIC inside the CPU.
PCI interrupts have arbitrary allocation by whatever BIOS sets things up and there's only 4 of them that are shared by other cards.
Message interrupts don't involve the legacy interrupt controller at all. I don't know if it is possible to program the PIC to trigger an interrupt in software, if so things would be possible with a software layer that sets up APIC which handlers then program PIC to generate an interrupt which is seen and handled by whatever DOS game etc. I'm not sure if the latency is unworkable or not.