It was low res, even pentiums stuggle with hi-res VESA modes 😀 I didn't run it for long, fiddled with different freq. oscillators, benchmarked it a bit and reassembled original setup. I believe 3.3V CPUs could work at 5V for months if used for typical home tasks, but if it ran in a 24/7 server machine, such CPUs would fry in a matter of days or weeks due to accelerated electromigration.

Indeed, most of the time it's better to stick to 40MHz FSB with stock cache, especially in PCI MBs.

I could only give bench results from tests done on UM486V with AMD DX4:

Vid. card - CL-GD5428 (Genoa 8500VL);
Chipset - UMC UM82C482/UM82C481/UM82C206F;
L2 cache - 256kB 20ns, async.

Doom 2 v1.666 time demo 2 (2001 gametics), hud on, high quality, no sound, clean DOS boot:

108.6MHz (54.3x2) - 1785 realtics (L2 read @ 3-2-2-2WS, write @ 1WS / DRAM read @ 1WS, write @ 0WS);
108.6MHz (54.3x2) - 1866 realtics (L2 read @ 3-2-2-2WS, write @ 2WS / DRAM read @ 1WS, write @ 1WS);
120MHz (40x3) - 1930 realtics (L2 read @ 3-1-1-1WS, write @ 1WS / DRAM read @ 1WS, write @ 0WS).

Note, that L1 was in "Write Through" mode all the time. I've just found out, that there is an internal pull-down on L1 cache selection pin of AM486 DX4-100...

I've used this pinout diagram from AMD's datasheet of DX2/4 CPUs:

pin R17 "CLKMUL" sets the multiplier, and pin B13 (which I've missed) sets either WB (high) or WT (low) L1 cache mode. Any idea how much of a performance boost would it be in WB mode @ 120MHz? Would it increase FPS at least by 2 in Doom's timedemo?

Edit: corrected benchmark results.

Single-banked cache on this board is probably limiting your use to 3-1-1-1 for the cache speed selection at 40 MHz.

L2 cache in WB mode has almost no effect on 486 boards. I'd be impressed with 1 fps increase in DOOM.

feipoa wrote:

Single-banked cache on this board is probably limiting your use to 3-1-1-1 for the cache speed selection at 40 MHz.

L2 cache in WB mode has almost no effect on 486 boards. I'd be impressed with 1 fps increase in DOOM.

UM486V's L2 cache is double banked (eight 32kx8 ICs). I'll try to rerun tests with cache set to WB mode, by the way, isn't cache writing protocol affecting only internal L1 cache?

Many boards have the option to set L1 and L2 cache types independently.

Jumpered interposer board for WB cache mode. PC posts, but stops loading into DOS just before when it should display a command prompt. PC at that point is not dead frozen, it still accepts inputs from keyboard and can be reset from "alt+ctrl+del" key combination. When turbo switch is toggled, PC simply halts, when turbo is untoggled, PC returns to normal operation. When internal cache is disabled, PC boots into OS normally. Did these tests at default FSB, and BIOS settings.

I wonder if this issue is caused by old BIOS, incompatible chipset or both. What else could be tried to make WB cache mode work on this motherboard?

OK, looks like I'm out of luck here. For L1 to operate in WB mode, chipset needs to support these 3 new signals from "Enhanced" 486 CPUs: /HITM, INV and /CACHE. Knowing that "Enhanced" 486DX2 (P24D) was announced only in 1994, while UM82C481 chipset was introduced in 1992 or in the beginning of 1993, I can safely conclude, that it doesn't support WB cache mode at all...

All 4 signals, including WB,/WT are N.C. in UM486V's CPU socket.

Source: WB mode requirements.