VOGONS


Reply 40 of 63, by DistWave

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I found this thread today. It seems that I got the same kingston sx/now upgrade to make similar experiments. I replaced the 386sx with a TI486SXLC40 (5v part, it can run in a 40 MHz or 20 MHz system ,with 2x internal clock multiplier)

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This cpu runs really hot a lot more than the original 386sx... I'd put a heatsink. It has the metal pad below, but it is not making contact with the PCB.
The main problem is that when I enable the internal 8kb cache I get an "A20 hardware error" and the system hangs (tested in a generic 286 12 MHz PC motherboard with SUNTAC chipset). The "external" 16 kb cache present in the upgrade can be enabled without problems.

Reply 41 of 63, by Paralel

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It's because it doesn't have support for Cyrix/TI's implementation of A20M#, Address Bit 20 Mask. It's not part of the typical pin out of a 386SX, as such, the pin on the SXLC-40 that would assert A20M# is likely not connected (N/C). If you have a scope, you can easily check it, but even a simple multimeter should work, since it has an internal pull-up resistor.

A20M# is asserted when internal processor cache is accessed. Without it, you would get an A20 error, so you can't use internal cache.

You may be able to connect the A20M# pin using a patch wire, but, that goes beyond my abilities.

Reply 42 of 63, by Deunan

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Connecting A20M is the best solution but might not be possible if that function is internal to one of the 286 mobo ASICs. But there is a software workround, the control registers on Cyrix/Ti have a bit to disable caching of the first 64k of every 1MB segment - that should fix this issue but obviously at a performance cost.

Reply 43 of 63, by CuPid

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hello guys,

I've just installed a system based on a Opal LX mainboard equipped with an IBM 486 SLC2-50 .
This little processor is simply amazingly fast. The board can do 20, 25 and 33 MHz FSB, and the CPU runs easily at 66 MHz with a small aluminium cooler. At that speed it is really fast in comparison to a classic Intel 486, considering its 16-bit external bus and the lack of L2. But of course, when floating point is involved, this is a different story.

Anyway, the CPU supports the MSR register from 1000h to 1004h, that surprised me because I thought that only the BL3 was supposed to support 1004h.

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I need a vacation.

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Reply 44 of 63, by RayeR

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Hi, what is the current status of this project? Did you managed to replace 386SX by 386/486SLC? I'm a bit confused of ambiguous informations readed aroud it is or not pin2pin compatible.
I just made an experiment of replacing intel 386SX-20 by IBM 386SLC on one MB and it didn't even POST. I did it mainly because I wanted to test the IBM 386SLC if it's OK so it makes situation harder because I don't know if CPU is OK and don't know (how much) is it compatible. I looked around for the datasheet and seems like you and I didn't find anything about IBM 386SLC. So can anybody tell if it has the same pinout like Cx486SLC already posted on 1st page?
https://i.imgur.com/oa7ImsC.png
If I assume yes, there are few new pins on SLC that are NC on SX. I didn't read anything about presence of internal pull up/down resistors so probably this pins should not be floating. But not clear to me how to wire all those inputs? They are mostly about cache control and suspend power mode so it seems to not be anything critical that should prevent CPU to POST so I would expect problems later when enabling the cache.
KEN# - enable cache, for test I'd pull up to disable
FLUSH# - invalidate cache input - how to generate this signal? for test I'd pull up or shouldn't matter when KEN# disabled
A20M# - mask for A20 (force low) - how to generate this signal? shouldn't prevent POST, I guess necessary when accessing memory beyond 1M, how to generate it?
SUSP# - enter suspend mode, should be pulled up to keep operating. My CPU was quite warm so I doubt it ended in suspend mode.
I'll have to beep this NC pins how they are wired on the MB.
There are also output pins RPLSET, RPLVAL, not sure if needed for some cache logic and SUSPA - acknowledge for SUSP, mostly not needed when SUSP disabled...

And for 286 to 386/486SLC upgrade module, does it mean it cannot work with enabled cache? Why then would they made it with SLC CPU when they could use cheaper SX without cache? Or is it some BIOS specific if cache will work (need to configure some MSRs and/or chipset registers)?

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Reply 45 of 63, by RayeR

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I measured the "NC" pins on IBM 386SLC and found there are differences compared to Cyrix datasheet. Interesting is that on SLC/Now! upgrade module there is only pin 43 connected to FPGA and others are NC, see table at bottom of page
http://rayer.g6.cz/hardware/sunta286.htm#386SLC_PINS

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Reply 46 of 63, by Anonymous Coward

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Cyrix and IBM SLC chips are not related to each other and have different pinouts. The IBM 386SLC may even be a low voltage part.

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V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium

Reply 47 of 63, by RayeR

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OK, anybody found IBM SLC datasheet?
But regardless some pinout differences on the upgrade module those extra pins was left floating except pin 43 so I think there should be good chance to make it working in 386SX board. Why do you think it may be 3,3V part? The voltage regulator is not populated on the module. As this modules was made also with 486SLC then there was used voltage regulator but not for this CPU, it's 5V powered.

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Reply 48 of 63, by furan

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RayeR wrote on 2021-04-08, 01:47:

OK, anybody found IBM SLC datasheet?
But regardless some pinout differences on the upgrade module those extra pins was left floating except pin 43 so I think there should be good chance to make it working in 386SX board. Why do you think it may be 3,3V part? The voltage regulator is not populated on the module. As this modules was made also with 486SLC then there was used voltage regulator but not for this CPU, it's 5V powered.

I’m not sure what you missed, but it’s a 3.6 v part with 5v tolerant IO.

Reply 49 of 63, by RayeR

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furan wrote on 2021-04-08, 07:49:

I’m not sure what you missed, but it’s a 3.6 v part with 5v tolerant IO.

Please can you post some source of this information? And if it is valid exactly for CPU IBM marked "33G0275" ? There are no any detailed informations. If it is true then Kingston violated the specification and fed the chip with 5V directly. I doubt so because they prepared the module for mounting a LDO so I suppose they would use is if needed.

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Reply 50 of 63, by furan

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RayeR wrote on 2021-04-08, 11:10:
furan wrote on 2021-04-08, 07:49:

I’m not sure what you missed, but it’s a 3.6 v part with 5v tolerant IO.

Please can you post some source of this information? And if it is valid exactly for CPU IBM marked "33G0275" ? There are no any detailed informations. If it is true then Kingston violated the specification and fed the chip with 5V directly. I doubt so because they prepared the module for mounting a LDO so I suppose they would use is if needed.

Simply measure on any IBM Alaris motherboard or SLC Thinkpad. I can’t find a photo of an SLC Now without the LDO installed. My upgrade worked, but the only reason it worked was that I raised all VCC and fed it 3.6v separately.

Reply 51 of 63, by Anonymous Coward

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The reason I'm not sure is that the 386SLC is pretty rare. The 486SLC was definitely a 3.x volt part, but the 386SLC predates that, so it may have still been a 5V part...or maybe not.
The pinout on the 386SLC and 486SLC should be the same though.
I think feipoa may have the pinout for the 486SLC. Check with him.

"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium

Reply 52 of 63, by RayeR

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>furan
Here's photo of my upgrade module
http://rayer.g6.cz/hardware/suntac.286/mb286d.jpg
As you can see VR1 is missing and the CPU is routed directly to 5V. On the photo is intel 386SX soldered on because of testing, I don't have a photo of IBM chip right now but I can take and post it tonight...

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Reply 53 of 63, by furan

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I guess I'm confused - if the module has the Intel chip, that explains why they're not doing the LDO thing - that's a 5v chip. Do you have a second module that has the IBM chip and also no LDO? Thanks - sorry for the confusion.

Reply 54 of 63, by RayeR

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No, the original module had IBM CPU but I have suspection, that the module is damaged. So I desoldered IBM CPU and tried to test it in 386SX board. Also I soldered working intel 386SX CPU on the upgrade module but it doesn't work either.

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Reply 55 of 63, by RayeR

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Here's photo of the upgrade module with IBM CPU before I swapped it by intel
http://rayer.g6.cz/hardware/suntac.286/slcnow1.jpg

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Reply 56 of 63, by feipoa

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Paralel wrote on 2020-05-10, 21:23:

It's because it doesn't have support for Cyrix/TI's implementation of A20M#, Address Bit 20 Mask. It's not part of the typical pin out of a 386SX, as such, the pin on the SXLC-40 that would assert A20M# is likely not connected (N/C). If you have a scope, you can easily check it, but even a simple multimeter should work, since it has an internal pull-up resistor.

A20M# is asserted when internal processor cache is accessed. Without it, you would get an A20 error, so you can't use internal cache.

You may be able to connect the A20M# pin using a patch wire, but, that goes beyond my abilities.

If my memory is right, normally I see A20M# on the processor connected to Gate A20 on the keyboard controller, at least for motherboards which tend to be Cyrix-aware. If not connected, a patch cable is fairly straight forward to solder on. Does this sound right to you?

Deunan wrote on 2020-05-10, 22:13:

Connecting A20M is the best solution but might not be possible if that function is internal to one of the 286 mobo ASICs. But there is a software workround, the control registers on Cyrix/Ti have a bit to disable caching of the first 64k of every 1MB segment - that should fix this issue but obviously at a performance cost.

That register has solved a lot of my problems, particularly with DMA SCSI and running Windows. If memory serves, there is not a similar register for the IBM BL3.

RayeR, I'm pretty sure I don't have the IBM SLC pinouts. That datasheet is about as rare as UMC databooks. I should have only the register settings and whatnot from the text already quoted in this thread. I've tested the IBM BL3 quite a bit and it is tricky to find a MB that works with it and it's L1 cache, especially in Windows. I was wondering, do we know with any certainty that its pinout is different from Cyrixes SLC? Has anyone tried to solder on an IBM chip to an interposer board which contains a Cyrix SLC chip? I have one of these that I've been wanting to experiment with, but it will have to wait for COVID to leave our life. Evergreen 486 SuperChip - settings for DIP switch?

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Reply 57 of 63, by RayeR

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feipoa wrote on 2021-04-09, 07:52:

do we know with any certainty that its pinout is different from Cyrixes SLC?

I'm pretty sure they are not 100% identical. According my table you can see differences of pins that have internal pull ups. This pull ups can be measured with DMM between IO pin and VCC pin and I see value about 18.5kohm that coresponds with cyrix datasheet that describes which input has internal pull ups. On the IBM CPU some pull ups are on different pins so I guess that there's also different direction of these pins, that one is input on cyrix maybe output on IBM and vice versa. But as I wrote most of these pins, except 43, was left unconected on upgrade module so I think they are not necessary for operation. I guess on IBM the pin 43 may be A20M#, that would make a sense this signal would be generated by FPGA from 286 signals...

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Reply 59 of 63, by Deunan

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RayeR wrote on 2021-04-09, 14:36:

I'm pretty sure they are not 100% identical. According my table you can see differences of pins that have internal pull ups. This pull ups can be measured with DMM between IO pin and VCC pin and I see value about 18.5kohm that coresponds with cyrix datasheet that describes which input has internal pull ups. On the IBM CPU some pull ups are on different pins so I guess that there's also different direction of these pins, that one is input on cyrix maybe output on IBM and vice versa. But as I wrote most of these pins, except 43, was left unconected on upgrade module so I think they are not necessary for operation. I guess on IBM the pin 43 may be A20M#, that would make a sense this signal would be generated by FPGA from 286 signals...

IBM and Cyrix 386 replacements have cache control lines on different pins, but are otherwise identical as far as I can tell. The reason why you couldn't get 386SX work in place of IBM chip might be down to voltage, Intel needs 5V - but AFAIR there were some 3V3 models from both Intel and AMD to be used on laptops. Or try a 5V version but on way slower clock (8MHz in, so 4MHz effectively - just to test the module). You probably want AMD anyway as most Intel's 386 were dynamic and could not be clocked lower than some 2MHz, whereas AMD is fully static design and can have the clock eveb stopped if needed.

Anyway, if only one extra line is connected then I bet you it's a cache flush signal. You don't need to worry about A20 mask unless you support proper per-line cache invalidation (and that's a few extra signals, including A20M), and most of these add-on modules do the very minimum to have any cache working at all. It's also usually the only thing possible anyway, there's too many different systems out there. The way it works is the cache is flushed, whole, on each DMA bus request. This can pretty much nullify any cache performance uplift (or even downgrade it - the flush is not a free operation) if the mobo uses pseudo-DMA to get CPU off the bus for DRAM refresh cycles (like in IBM XT). So you either need a so-called hidden refresh (some BIOSes/mobos offer it) or some extra logic on the add-on to try and figure out which "DMA" is actual one and which is just refresh.

With just cache flush impemented, and a bog standard 386SX in place of IBM chip, the module should work (with no cache or performance uplift obviously). I don't really see why it wouldn't unless this signal is some weird bi-dir, but before concluding that I'd blame wrong VCC, clock, and possible damage to the PCB first.