VOGONS


1024k L2 Cache- where can I find it?

Topic actions

Reply 20 of 28, by Nitroraptor53

User metadata
Rank Member
Rank
Member
dionb wrote on 2020-02-27, 19:15:
Nitroraptor53 wrote on 2020-02-26, 23:23:
mpe wrote on 2020-02-26, 22:40:

Ridiculous is 128MB RAM in my Macintosh SE/30 (1989 system).

64MB RAM wasn't that uncommon in 486 days if you were doing stuff like DTP in Aldus Pagemaker or QuarkXPress.

How on God's Green Earth did you get that much RAM on an SE/30? Accelerator Card?

Regular SE/30 has 8x 30p SIMM slots. Populate them with 16MB SIMMs and you get 128MB. I did the same when I briefly had an SE/30 back in the 00's.

I didn't think an 80's machine would have native support for 128mb's!

Reply 21 of 28, by Nitroraptor53

User metadata
Rank Member
Rank
Member
cyclone3d wrote on 2020-02-27, 19:09:

How much cache does the system support?

How much does it currently have?

How many sockets does it have?

8 sockets, 0 chips, no cache. No idea how much the board supports, it's a late (er) mobo though.

Reply 23 of 28, by root42

User metadata
Rank l33t
Rank
l33t

That wouldn’t work now, would it? The extra pins are probably for addressing. Well maybe it would work, but you would waste capacity of the SRAM.

I would loom up the board and its manual and then try to hunt down the correct ICs.

Edit: http://ps-2.kev009.com/pcpartnerinfo/ctstips/fa2a.htm

Edit 2: this one would fit I think:
http://www.raphnet.net/electronique/nes_vs/as7c256-20pc.pdf

YouTube and Bonus
80486DX@33 MHz, 16 MiB RAM, Tseng ET4000 1 MiB, SnarkBarker & GUSar Lite, PC MIDI Card+X2+SC55+MT32, OSSC

Reply 26 of 28, by Tiido

User metadata
Rank l33t
Rank
l33t

64 and 128KB chips are all 32 pin, 28pins tops at 32KB.

T-04YBSC, a new YMF71x based sound card & Official VOGONS thread about it
Newly made 4MB 60ns 30pin SIMMs ~
mida sa loed ? nagunii aru ei saa 😜

Reply 28 of 28, by Disruptor

User metadata
Rank Oldbie
Rank
Oldbie

You require 8 1 MBit SRAM chips as cache plus 1 512 KBit SRAM chip as tag.
I run a 256 MB 486 with 1024 K L2, so all DRAM is cacheable when running in write-through.

My 486 UMC8886/8881 Project (Version 2.0)

Even with less DRAM you feel the difference. It's just because the cache hit rate increases.