In order to support write back it is necessary to store some information somewhere about which cache line is modified. This is in order to be able to write it back to RAM in case something else than the CPU would want use it (so called cache coherency).

Given most 486 era SRAM chips are 8 bits wide there isn't enough space in the normal tag chip for that information. That's why many motherboards used a dedicated chip for that purpose.

Also as you only need 1 or 2 bits of extra information per line some more modern chipsets maintain that information inside the chipset and can avoid having an external chip altogether. Or they use a wider tag chip. Or do some sort of cacheable range tradeoff.

While some write-back implementations can work even without any dirty or alter tag they don't have optimal performance as they need to flush the cache more often than needed which can actually decrease the performance over a simple WT.