No cache wasn't so much a thing of that vintage but of a particular - bottom feeder - market segment. It started as soon as motherboard cache started going mainstream in later 386 era and continued until even Intel got into the game later (briefly) with the Covington Celeron.
As for So5 and cache, it depends which cache. Early So5 used asynch cache, which was better than nothing, but gave at best a few percent better memory performance. Later So5 started using PLB cache, which dramatically improved preformance, with up to 20% higher memory scores and - depending on the application - high single digit to low double digit percentage improvement in application performance.
Because PLB was so useful, but also so expensive, So5 was the era of the COAST slot, allowing boards to ship with cheap asynch (or no L2 cache at all) but to advertise "PLB-ready".
As for the amount, it depended on chipset, some supported up to 1MB (officially; 2MB might be possible unofficially on some SiS chipsets), but except in a very small set of applications, performance didn't scale much past 512kB and the ubiquitous 256kB gave you most of that boost already.