I'm thinking of getting one of those Cyrix/TI 486DLC chips for my 386DX-33 machine. Do they require specific chipsets to work or should they work with any machine of the era? I don't know what chipset I have, just that the board seems to have been made in either 1991 or 1992 based on the BIOS date.
Chipset isn't the main thing, it's about circuitry for cache coherence. Bottom line: if your board doesn't support it, it's not likely to work well.
To avoid that, you can try to find a Cx486DRx2. That's not only faster, but has the circuitry integrated into the CPU package, so it should work on any 386 board. Rare and pricey though, unfortunately.
But let's see if we can identify that board. 1992 is when the DLC was released, so it's possible (if unlikely) that the board might support it natively.
I need to get the battery off that board anyway, it wasn't leaking a few months ago but that was a few months ago.
Most of the boards that natively support the DLC are supposed to use the #FLUSH pin on the CPU to keep the L1 cache coherent. Boards that don't support it natively are supposed to use the BARB method to keep the cache from going stale, but as far as I know BARB only works properly if your board supports "hidden refresh". For the most part the DLC will work on boards made after 1990. The older 386 boards might be more hit or miss.
For example, I have a CTI 386 motherboard from 1990 that refuses to even POST with the DLC installed. However, some people use DLC chips on Intel Inboard 386/PC, which is an 8088 upgrade product from 1987 or so...not sure if they had to be modified first.
"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium
Preferably you need 2 things:
1) BIOS support for 486, even if it's just for the SLC/DLC
2) All 3 signals KEN#, FLUSH# and A20M# connected
Now, without BIOS support the mobo might not even boot. That'a a major problem. If it does boot but doesn't support/recognize the CPU it'll work but most likely none of the signals mentioned are connected.
Of the 3 signals KEN# could be missing, in that case a software needs to be run to properly configure Cyrix cache exclusion zones, but with just FLUSH# and A20M# you'd still get pretty much 100% performance. If A20M# is missing you need to enable another workaround that, depening on where the code is loaded, can be costly in terms of performance. Without FLUSH# you have use BARB setting as mentioned above and if the mobo doesn't have hidden refresh option but instead just enters bus hold (like for DMA) every 15us then the cache is next to useless.
There's still some 10% or so improvement (might be much higher on code heavily based on multiplication, which Cyrix does in 1/4 of the time even for a typical 486 core) from just the pipelined 486 core. Especially with zero-waitstate RAM. But that's usually not really visible in many game, just the benchmark programs.
