I don't see where your "RAM must wait for cache" claim comes from. There is no reason for the L2 cache to not accept a cacheline fill (this is what happens on a read miss) as fast as it can do a read burst. So if the cache can do 3-2-2-2 at 50MHz when the processor reads from it, it should be perfectly fine to capture data from the RAM at 5-2-2-2 when the processor fills a cacheline from RAM.

There is no strict requirement that a chipset must not put the row address of a potential RAM cycle already onto the memory address bus (or the column address in case of a page hit), if it does not start the cycle using /RAS or /CAS, so there also is no need for the lead-off to be slower on boards with L2 cache than on boards without L2 cache. Still, you can make the trade-off of not[ starting a RAM cycle before you know you have a cache miss to prevent unneeded closing of pages.

As I understand it, the main problem that hindered EDO adoption in PC systems is a shortcoming of the PS/2 memory module system. To make use of the the page mode (which you do want starting at FSB above 10 MHz), you want to keep open memory pages for some time. This is a simple thing on FPM RAM: Just don't de-assert the /RAS line to keep the page open. Keeping /RAS asserted does not cause any complications on the board when you use FPM RAM (of course, you can't refresh RAM while a page is still open, and some other complications inherent to DRAM architecture). On EDO DRAM on the other hand, the "extended data out" phase has the modules drive the memory contents to the data bus as long as /OE (output enable) and /RAS (row address strobe) keep asserted. So while you can cause an FPM module to release the data bus by just deasserting /CAS, the whole point of EDO is that you can't. So to free the data bus with EDO modules, you need to either deassert /RAS or /OE. And that's where the shortcoming of PS/2 modules is apparent: /OE is no pin on PS/2 modules, and the /OE input pin of EDO chips is permanently asserted! This means the only way to have an EDO PS/2 module stop driving the data bus is deasserting /RAS, which causes the module to close the page.

This means for EDO support on PS/2 modules, you can only have one bank open at once, and if you don't have buffer chips between RAM and the FSB (although you always should), you can't even have a single page open if any other bus cycles of the processor is going to happen. One of my long-term plans is connecting the /OE input of the memory chips of a PS/2 module to one of the reserved or the presence detect pins of that PS/2 module, and add a bodge wire from the /MEMOE output of the SiS 496 north bridge to that pin on the PS/2 slot. This could fix the incompatibility with EDO modules known for a lot of 486 mainboards.