PlaneVuki wrote on 2020-08-18, 11:26:Thanks for the reply. […]
Show full quote
Thanks for the reply.
I think you have a slight mistake there, If I checked the manual correctly:
BHE=0 and BLE=0 >>> 16bit transfer
BHE=1 and BLE=0 >>> 8bit transfer via D0-D7
BHE=0 and BLE=1 >>> 8bit transfer via D8-D15
BHE=1 and BLE=1 >>> this is invalid signal, doesn't happen
That's the 386SX bus interface, which is often believed to be identical to the 80286 bus interface. It is not identical! The 80286 does not have a BLE signal, but it has an A0 signal instead. It uses the following table:
A0=0 and BHE=1 >>> 16bit transfer
A0=0 and BHE=0 >>> 8bit transfer via D0-D7
A0=1 and BHE=1 >>> 8bit transfer via D8-D15
A0=1 and BHE=0 >>> this is invalid signal, doesn't happen
PlaneVuki wrote on 2020-08-18, 11:26:Are you saying that, for pure 8bit system (except cpu of course), I need some kind of controller and latches to handle 16bit tra […]
Show full quote
Are you saying that, for pure 8bit system (except cpu of course), I need some kind of controller and latches to handle 16bit transfers?
I checked the chips on IBM AT and can't see which of them could be doing this.
Surely not the 82288 I think ?
So how does IBM AT does this ?
The technical reference manual for the 5170 is available on minuszerodegrees, schematics of the AT mainboard ("planar") type 1 start at page 92 (linear page count) aka page 1-76. Central components are
- the registered bus transceiver 74LS646, U67, on sheet 2 (it can latch the low 8 bits)
- the PAL 16L8, U87 on sheet 6 (generates the control signals)
- the transceiver 74LS245, U102 on sheet 13 (it forwards low-to-high or high-to-low on the system bus)
- the logic on the lower half of sheet 12, involving DATA CONV, CONVA0 and CONVALE. This logic uses clocked flip-flops to sequence the two sub-cycles.
PlaneVuki wrote on 2020-08-18, 11:26:If it really not possible to do by "simple" means then too bad.
I was really wished that it was possible. […]
Show full quote
If it really not possible to do by "simple" means then too bad.
I was really wished that it was possible.
Edit: Also, in fact 80286 does a 16bit transfer using 2x 8bit transfers, natively, but only if trasferring a word to (not from!)an address that starts with odd.
Already so much complication but not very useful for a system designer, what were they thinking when designing these cpus.
Would be really nice to have a "286sx" with native 8-bit data bus.
All word cycles to odd addresses (misaligned word cycles) get split by the 286, both reads and writes. I already alured to that in my previous post by suggesting a misaligned stack to prevent 16-bit operations from happening. In the Am80286 datasheet, it is written on page 1-96, below the head-line "Physical Memory and I/O interface", bold-face emphasis mine:
80286_Datasheet wrote:
...while odd-addressed words require two bus operations. The first transfers data on D15-D8, and the second transfers data on D7-D0. Both byte data transfers occur automatically...
PlaneVuki wrote on 2020-08-18, 11:26:
Would be really nice to have a "286sx" with native 8-bit data bus.
Take a look at the 80188, if you don't need protected mode. There are embedded 80188 variants available today that use 256 byte segment spacing instead of 16 byte segment spacing, such that the addressable range is 16MB, just like on a 80286.