I've always wanted to try this. A 486 with no L2 cache and wirespeed main memory. I've seen chipset support for such a configuration in the SiS 401 so I know it's possible.
Looking for recommendations on a VLB chipset that will also offer this option - obviously the memory controller needs to be top tier. 72-pin SIMMs are also a must so I can find newer sticks that will tolerate ~40ns access timings
You need to specify what you mean by 0 WS.
RAM is not a directly connected static memory device and by definition needs a few cycles before the CPU can read from it (opening page, setting access strobes, closing, some stretching after read, occasional wait for refresh, etc. These operations needs one or more cycles depending on state of the machine and type of RAM/memory bus. So I don't believe a true zero-waitstate RAM operation is possible with DRAM on a 486 like system.
On a typical 33 MHz bus 486 it is typically 4 to 8 - 2-2-2. So four sequential memory transfers needs 10-14 (CPU wait state) cycles depending on initial state of the memory bus. Perhaps less if you run RAM cycles with more aggressive timing or outside of the specs.
I now that som BIOSes use 0WS, but it usually means "no extra waitstates" on top of nominal RAM cycle which can be anything. So 1 WS usually means 4-3-3-3, but the bios maker can use any definition.
I think most non-overclocked well functioning motherboards with quality RAMs should be capable running at 0 WS (4-2-2-2) at 33 MHz.
I mean 2-2-2-2, the same way a 0WS 286 system would access main memory
Not sure. Perhaps one of these elusive Octek DCA boards? They shipped with special low latency RAMs and had no L2. Or a motherboard designed for 16-20 MHz bus?
A typical 486 chipset supports 25 MHz+ and can be programmed down to 3-2-2-2 with zero one or more of extra cycles.
The SiS 401 chipset has the type of setting I'm looking for, they call it "turbo DRAM" or something and specify its use with 25MHz or less FSB
On the other hand the extra saved cycle would likely have a negligible performance difference. Especially on a cached system.
mpe wrote on 2020-09-26, 17:42:On the other hand the extra saved cycle would likely have a negligible performance difference. Especially on a cached system.
I'm not sure I believe that. Would like to try it out and see
there was some guy with a 486 based on static ram alone - the only comparison i can think of; i cant recall the name though
