they're probably two slightly different chips

Oh, that used to be called piggy-back style, I believe.
In simple words, all chip lines are in parallel, except for two address decoding pins - these two are in series (the cards memory address logic connects to the input of RAM a and the output of RAM a goes into input of RAM b; while output of RAM b in turn goes to input of RAM c and so on).
That way, the addressing goes through all the RAM chips..

Edit: Small edit.

imi wrote on 2021-02-09, 00:52:

they're probably two slightly different chips

It is a different part number on the top chip vs. the expansion daughtercard. Maybe you're right.

keenerb wrote on 2021-02-09, 02:13:

imi wrote on 2021-02-09, 00:52:

they're probably two slightly different chips

It is a different part number on the top chip vs. the expansion daughtercard. Maybe you're right.

Most DRAM chips have the bits in a square matrix of rows and columns, where both the row count and the column count is a power of two. So you can get 4k, 16k, 64k or 256k addresses inside one
chip. The piggy-back chips are the missing steps of 8k, 32k or 128k. In this case, the capacity is distributed over two chips of the conventional size. Usually, the lower and the upper chip use different pins for "/RAS" or "/CAS", which work similar to a chip select signal. In fact, the setup is very similar to double-sided PS/2 SIMMs. Double-sided PS/2 SIMMs (technically: dual-rank SIMMs) also have all the data and address lines of the chips from both sides in parallel, they only have /RAS or /CAS split for both sides.