That's awesome! Unfortunately I do not know exactly myself how to utilize 50ns in the boards I own. I use 60ns RAM and have no issue setting to tightest memory settings in the BIOS. I hope someone else can shed some light on this.

50ns modules would be really helpful for people like myself building hotrod 286 systems. At 0-ws, 25MHz is really pushing the limit of 60ns modules (I have 2 sticks out of a dozen or so that run stably enough to get benchmark data at that speed). I'm not sure anyone has been able to achieve 30MHz without wait states.

Unfortunately the amount of 286 boards that can take 4MB SIMM modules is very, very limited. Most only accept 256KB or 1MB densities.

do you happen to know if these NOS infinion 50ns parts are available in a 1Mx1 organization?

megatron-uk wrote on 2021-02-21, 15:26:

50ns modules would be really helpful for people like myself building hotrod 286 systems. At 0-ws, 25MHz is really pushing the limit of 60ns modules (I have 2 sticks out of a dozen or so that run stably enough to get benchmark data at that speed). I'm not sure anyone has been able to achieve 30MHz without wait states.

Unfortunately the amount of 286 boards that can take 4MB SIMM modules is very, very limited. Most only accept 256KB or 1MB densities.

Thank you for the information!!
I have zero experience with 286 machines.
I could have never guessed that these modules might be useful there.
If there is a significant demand I can probably make some 1MB-50ns-FPM ones!

maxtherabbit wrote on 2021-02-21, 15:44:

do you happen to know if these NOS infinion 50ns parts are available in a 1Mx1 organization?

No idea, I have to research this. Even these 4Mx1 and 4Mx4 were rely hard to find.

Are you planning to sell these? At the right price I may be in for a couple of kits.

these look nice! Will you sell any? interested as well

Overclocked 286 would benefit from faster memory modules. For this I have eight 45ns chips (1MB) prepared... I just need "little" free time - project is on hold ~three years now 🙁

As I said in the video, for now I only have a few 4x4MB kits.
To be exact 5 of them. I want to keep 2 for myself. So 3 are available.
I will only do one kit per person for now and ideally to people that can really use them.
I would probably make more in the end, but the stock for these chips is questionable.

Now regarding pricing.
These are premium 50ns modules. No one sells something like that so I can not compare.
I am located in Europe. The cheapest kits I see in ebay are at 32e and these are 70ns.
To my understating, one previews attempt here in Vogons was at 36e per kit (60ns, no parity chip).

So I am thinking that 60e for these kits is a fair price (15e per 4M module).
This might sound high to some people, but in the end these are not your standard modules.

Good news guys.
I found stock on some sick 40ns FPM 5v 1Mb chips.
So in about 1 month from now...
if everything goes well...
expect some 1MB simm-30 40ns FPM modules from me.

The drawback is that I will have to skip the parity chip this time 😒
I know this is a problem with some boards... but well, this is 40ns FPM :p

Sounds good.
Render me interested. 😀
Looks like at least 5-10 orders already.

galanopu wrote on 2021-02-23, 18:50:

Good news guys. I found stock on some sick 40ns FPM 5v 1Mb chips. So in about 1 month from now... if everything goes well... exp […]
Show full quote

Good news guys.
I found stock on some sick 40ns FPM 5v 1Mb chips.
So in about 1 month from now...
if everything goes well...
expect some 1MB simm-30 40ns FPM modules from me.

The drawback is that I will have to skip the parity chip this time 😒
I know this is a problem with some boards... but well, this is 40ns FPM :p

are these SIMMs going to be 2 chips of 1Mx4 or 8 chips of 1Mx1 organization?

the types of early 386 and 286 boards that would benefit from these fast modules often cannot refresh the 2/3 chip SIMMs properly

How are there problems ? There's exact same amount of CAS pages and thus refresh cycles between the two organizations.
If anything, 8/9 chip sticks propose challenges due to increased loading on the bus due to way more capacitance per signal which will bring rise and fall times down...

Tiido wrote on 2021-02-24, 02:34:

How are there problems ? There's exact same amount of CAS pages and thus refresh cycles between the two organizations.
If anything, 8/9 chip sticks propose challenges due to increased loading on the bus due to way more capacitance per signal which will bring rise and fall times down...

honestly I don't remember the details, but I promise you it's a real thing - we have had threads about it on VCFED

some motherboard documentation of the time even mentions it

I have some 9 chip 1MB 60ns SIMMs that are just marginal at 25MHz - on their way are some 3 chip versions which I hope to be more successful; I don't know about it the electrical characteristics of these boards but at the very least the lower physical density and increased spacing between packages should be better from a thermal management perspective.

Form what I have read... some 3 chip versions have problems with some very old M/B.
But the problem is usually with the parity function and this makes sense as the 3rd chip is different and has marginally different timings.
Now from an electrical point of view... 8x1Mx1 or 2x1Mx4... I do not think any motherboard can understand the difference.
The only potential problem is if the 1Mx4 are just newer chips and have extra type of transfer / refresh cycle that is not supported by older M/Bs.

Now what I am gone try here... is test my luck with some 1Mx8bit chips!
So a single chip per module and probably the only way to get 40ns.
That is why the first batch will be again only 20 modules. Worst case I will blew a few 100e here.

I am also in contact with the "cpu galaxy" youtube channel. We live in the same city. He is a very nice guy.
So he can give me probably some more old M/Bs for testings these or I will give him some of these for testing. :p

Tiido wrote on 2021-02-24, 02:34:

How are there problems ? There's exact same amount of CAS pages and thus refresh cycles between the two organizations.

While the addressing scheme looks like there is the exact same amount of CAS pages, the internal organization is different. It is very common for 1M x 1 chips to be internally organized the same as a 256K x 4 chip, where two address bits (often the highest row and column bit) are used to select which of the four 256K bit fields to use. The consequence is that many 1M x 1 chips (I randomly googled for a 1M x 1 datasheet, and the first one I found is The MB81C1000A) only need a 9-bit refresh counter even if they are addressed in a 10 x 10 fashion. On the data sheet I linked, the timing diagram for the RAS-only refresh explicitly states that the pins A9, WE and DI (data in) are "don't care", but must be at a valid high or low logic level.

On the other hand, all 1M x 4 chips need a 10-bit refresh counter.

It's in fact not something that is new with 1M x 1 chips. The same issue was already present with 64K x 1 chips, where some of them needed a 7-bit refresh counter (as provided by the Z80), while other of them needed an 8-bit refresh counter. -0° has a nice overview over the 64K x 1 chips that includes whether they have 128 or 256 rows to be refreshed.

Yes this is true! I did my research earier today.
All the 1Mx1 chips I checked were organised differently (9 x 11 bits), with sorter refresh cycles (512).
So unless the M/B refreshes up to the 10th bit this will not work with 1Mx4 or 1Mx8 chips (that are 10 x 10 bits).
Newer motherboards also support auto-refresh, so there is never a problem there.

In the end I also found stock of some 1Mx1 50ns chips.
The problem is that if I make 9-chip 1MB modules this will cost significantly more.
I will probably make them either-way for comparison.
However if I sell them these would be very expensive!

mkarcher wrote on 2021-02-24, 20:01:

While the addressing scheme looks like there is the exact same amount of CAS pages, the internal organization is different. It is very common for 1M x 1 chips to be internally organized the same as a 256K x 4 chip, where two address bits (often the highest row and column bit) are used to select which of the four 256K bit fields to use. The consequence is that many 1M x 1 chips (I randomly googled for a 1M x 1 datasheet, and the first one I found is The MB81C1000A) only need a 9-bit refresh counter even if they are addressed in a 10 x 10 fashion. On the data sheet I linked, the timing diagram for the RAS-only refresh explicitly states that the pins A9, WE and DI (data in) are "don't care", but must be at a valid high or low logic level.

On the other hand, all 1M x 4 chips need a 10-bit refresh counter.

It's in fact not something that is new with 1M x 1 chips. The same issue was already present with 64K x 1 chips, where some of them needed a 7-bit refresh counter (as provided by the Z80), while other of them needed an 8-bit refresh counter. -0° has a nice overview over the 64K x 1 chips that includes whether they have 128 or 256 rows to be refreshed.

Ok, this is interesting. I actually now remember dealing with this sort of thing before but with ancient hardware needing the ancient chips and it only mattered for RAS only refresh in that application. CBR refresh would have worked there though but it wasn't a thing for that hardware.

I would think that a board needing the small refresh count but can still support 4MB sticks are limited to only the early boards and there probably aren't a whole lot... I have only ever seen incompatibility on 286 boards but because they don't connect all the address lines and all my 386 and 486 boards have not had any issues with the 10bit refresh count requiring parts. I don't have any actually old boards though as far as 386 stuff goes.