weedeewee wrote on 2021-05-17, 19:15:

Deunan, for all I comprehend about the issues with the memory modules...

It tends to be a refresh issue.

Indeed. x4 chips (used on 3-chip SIMMs) typically need one more address bit for RAS-only refresh than x1 chips. x1 chips often ignore the highest address bit for RAS-only refresh, so boards not driving the highest address bit during refresh can work with 9-chip modules, but fail with 3-chip modules.

I am using this calculator 😉

http://www.knubbelmac.de/hardware/ram-kalkula … r.html#ergebnis

how rare are 4mb 30-pin simm modules? i have seen people in my country looking for some of those for years.

I was lucky enough to get 4 modules on a pc from a co-worker. gave it to me for free because he had it in the closet for 20 years. When i opened , it had a really bad motherboard, a nice graphics card but the gem was 4 sticks of 4mb each.

Its not about building a pc with those modules that im really interested on, those modules for me are a gem for soundblaster AWE32 , since you can expand the memory to 8mb

I wish it could be possible to make a memory transplant, its just 2 chips, take a 1mb stick and transplant some higher capacity chips in it while keeping the parity chip.

The layout of 4MB and 1MB SIMMs is different enough that transplanting high capacity chips doesn't make a lot of sense. We already had a thread about newly-made 30-pin SIMMs recently here, and getting PCBs from a manufacturer like PCBway or JLPCB seems like a better wat to go than using 1MB SIMMs as base. In Germany, I don't have any problems obtaining 70ns 4MB SIMMs, but a set of four might cost around 40€ if I'm impatient.

mkarcher wrote on 2021-05-17, 19:23:

weedeewee wrote on 2021-05-17, 19:15:

Deunan, for all I comprehend about the issues with the memory modules...

It tends to be a refresh issue.

Indeed. x4 chips (used on 3-chip SIMMs) typically need one more address bit for RAS-only refresh than x1 chips. x1 chips often ignore the highest address bit for RAS-only refresh, so boards not driving the highest address bit during refresh can work with 9-chip modules, but fail with 3-chip modules.

Thanks for the explanations ! I have a few old boards that do hate the 3 chip 30 pin simms but run well on the 9 chip.

mkarcher wrote on 2021-05-17, 19:23:

Indeed. x4 chips (used on 3-chip SIMMs) typically need one more address bit for RAS-only refresh than x1 chips. x1 chips often ignore the highest address bit for RAS-only refresh, so boards not driving the highest address bit during refresh can work with 9-chip modules, but fail with 3-chip modules.

Huh. Are you sure about this? Because having different row address length doesn't make much sense, even on boards that do work that would cause the "wider" chips to be refreshed at half the pace.
Why would the x4 chip even have a different row size? Let's consider a 1MiB stick, it needs either 9 chips of 1Mx1 or 2 chips of 1Mx4 plus 1Mx1 for parity. These are all 1M, thus 20 bits, thus the optimal (and only sensible) split would be in half to get exactly 10 bit for row and column. So in the end the row size is the same, no matter the number of inputs/outputs.

Can anyone list the chips on a 3-chip stick that doesn't work, when a 9-chip stick does? It should be possible to dig up datasheets and simply check what the row address length is. Unless for some reason the refresh uses less bits then addressing, but why? And more importantly how would that even work?

Deunan wrote on 2021-05-18, 00:01:

Can anyone list the chips on a 3-chip stick that doesn't work, when a 9-chip stick does? It should be possible to dig up datasheets and simply check what the row address length is. Unless for some reason the refresh uses less bits then addressing, but why? And more importantly how would that even work?

I believe I can. I have a VLSI 200 series 386sx machine that would 100% not work with 3 chip SIMMs. It was even specified as such in the documentation

i saw they are pricy on ebay. i wish i had some for all my soundcards.

here i cannot find them at a good price, and the 32mb simms is like impossible to get too. only 16mb, 8mb and 4mb. i know its an overkill for 486 era but some pentium boards only accepted edo simms, and if you want to go all the way up to win98 you need mote memory to hace a smooth experience

maxtherabbit wrote on 2021-05-18, 01:11:

Deunan wrote on 2021-05-18, 00:01:

Can anyone list the chips on a 3-chip stick that doesn't work, when a 9-chip stick does? It should be possible to dig up datasheets and simply check what the row address length is. Unless for some reason the refresh uses less bits then addressing, but why? And more importantly how would that even work?

I believe I can. I have a VLSI 200 series 386sx machine that would 100% not work with 3 chip SIMMs. It was even specified as such in the documentation

I also have a VLSI 386 board, an old Unisys 486 (5v cpu only) DX33 and Octek Headland chipset based 286 that does not like them, will have to dig em out to report the exact chipset models. Have yet to see any 286 that works proper with 3 chip simms though they may exist..

Deunan wrote on 2021-05-18, 00:01:

mkarcher wrote on 2021-05-17, 19:23:

Indeed. x4 chips (used on 3-chip SIMMs) typically need one more address bit for RAS-only refresh than x1 chips. x1 chips often ignore the highest address bit for RAS-only refresh, so boards not driving the highest address bit during refresh can work with 9-chip modules, but fail with 3-chip modules.

Huh. Are you sure about this? Because having different row address length doesn't make much sense, even on boards that do work that would cause the "wider" chips to be refreshed at half the pace.

It should be possible to dig up datasheets and simply check what the row address length is. Unless for some reason the refresh uses less bits then addressing, but why? And more importantly how would that even work?

I already dug up data sheets to support that claim, see Re: Custom made, 50ns, FPM, Simm 30, memory modules with parity.

mkarcher wrote on 2021-05-18, 05:08:

I already dug up data sheets to support that claim, see Re: Custom made, 50ns, FPM, Simm 30, memory modules with parity.

I have that datasheet. I also have the datasheet for MB814400A which is 4Mx1 and has 1024 refresh cycles.

So first, my bad, I was so focused on the row size that I didn't consider that longer also means shorter - depending on the point of view. However the mobo must supply the counter for the longest row chip - and it should, because it will be 9, 10, or 11 bits for 256k, 1M or 4M stick. So the 1MiB stick I picked as an example must get 10 bit counter, no matter what kind of chips are on it. Otherwise it won't work even with 9 identical chips either.

But here's the thing - the mobo counter should just count up in 16us intervals and that's it. It can be, say, 12 bits and that will support all chips at once. Why? Because the highest-order are don't care for smaller chips, the counter will internally just wrap around. And that's OK because the 1024-cycle refresh is 16ms, and the 512-cycle refresh is 8ms, which always divides to the same base of about 15-16 us.

So I fail to see how that scheme would break. It would only if the parity chip had longer row address than the data ones, and mobo was not driving all the address lines properly. But that's not the case here.

Deunan wrote on 2021-05-18, 09:09:

However the mobo must supply the counter for the longest row chip - and it should, because it will be 9, 10, or 11 bits for 256k, 1M or 4M stick. So the 1MiB stick I picked as an example must get 10 bit counter, no matter what kind of chips are on it. Otherwise it won't work even with 9 identical chips either.

But here's the thing - the mobo counter should just count up in 16us intervals and that's it. It can be, say, 12 bits and that will support all chips at once.

If the motherboard has enough bits, it will just work. The point is that 9-chip modules can deal with a missing highest bit, whereas 3-chip modules can't.

A board that has a 10-bit refresh counter will work with 9-chip 1MB modules (consisting of 1Mx1 chips that require a 9-bit counter). It will work with 3-chip 1MB modules, too. The 1Mx4 chips require a 10-bit counter, which is present. That board will also can refresh 9-chip 4MB modules, as the 4Mx1 chips deal perfectly well with the 10-bit refresh counter. Assuming the board supports 11x11 addressing, it can also correctly address and thus use the 9-chip 4M module. But it will fail on 3-chip 4M modules, because their data chips would need an 11-bit refresh counter.

A board with a refresh counter that is "one bit short" will thus support both 9-chip and 3-chip modules, except for 3-chip modules of the highest addressable size.

Ah, I get it now. Your point is the 1Mx1 modules are mostly refreshed with 9 bits accross the board? Possibly because it allows older HW with narrow counters for 256k chips to "just work", you only need to extend the addressing, and also it lets you manufacture such chips in older process (albeit with the requirement of having twice as many internal amplifiers - still worth it I guess).

So, I'm not aware of how (un)common 1Mx1 chips that require full 1024-cyle refresh are. But if such chips existed, and one would put them on a stick in 9x configuration, these would also fail - correct? It's only by the grace of having most of them use 512 cycles that we can say that 9 chip solution works but 2+1 one doesn't?

Deunan wrote on 2021-05-18, 09:54:

Ah, I get it now. Your point is the 1Mx1 modules are mostly refreshed with 9 bits accross the board? Possibly because it allows older HW with narrow counters for 256k chips to "just work".

[...]

So, I'm not aware of how (un)common 1Mx1 chips that require full 1024-cyle refresh are. But if such chips existed, and one would put them on a stick in 9x configuration, these would also fail - correct? It's only by the grace of having most of them use 512 cycles that we can say that 9 chip solution works but 2+1 one doesn't?

Yes, exactly that was my point. The reason that 1Mx1 chips use 9-bit refresh is that the die is nearly the same as the one in 256Kx4 chips. Basically both kind of chips work the same, It's just that the 1Mx1 chip outputs/inputs only one of the four bits. The amount of sense amplifiers is the same for both.

Interesting side note: Before page mode chips were common, there were some special "nibble mode" chips which are an interesting crossover between x1 and non-page-mode x4 chips. They have one data in and one data out pin, just like x1 chips, but when you add extra CAS cycles while keeping RAS asserted, it does not take a new column address (that would be page mode), but it cycles through the four bits a x4 chip would output at once.

Oh wow, my brain must be on vacation, or it's the weather maybe. I just couldn't process what you mean by 256kx4 until now. And yes, that makes sense - if I was to re-use 256kx4 die to make 1Mx1 then I'd also just add two flip-flops to store the highest order bit on both /RAS and /CAS and have that select a plane. The rest of the chip is pretty much identical. Why, it can even be done from the start and the configuration selected during bonding with one extra wire. You learn something new (well, old in this case) every day.

Horun wrote on 2021-05-18, 04:20:

maxtherabbit wrote on 2021-05-18, 01:11:

Deunan wrote on 2021-05-18, 00:01:

Can anyone list the chips on a 3-chip stick that doesn't work, when a 9-chip stick does? It should be possible to dig up datasheets and simply check what the row address length is. Unless for some reason the refresh uses less bits then addressing, but why? And more importantly how would that even work?

I believe I can. I have a VLSI 200 series 386sx machine that would 100% not work with 3 chip SIMMs. It was even specified as such in the documentation

I also have a VLSI 386 board, an old Unisys 486 (5v cpu only) DX33 and Octek Headland chipset based 286 that does not like them, will have to dig em out to report the exact chipset models. Have yet to see any 286 that works proper with 3 chip simms though they may exist..

Update: Both my DTK PEM3301 386 (VLSI 100 series chipset) and Unisys PW2 300/486 (VLSI 300/330 series chipset) boards use VLSI chipsets, appears a common factor in old boards that will not work with 3 chip 30 pin simms

Hi all,

I ended up on this thread as I had a more or less identical situation; a big pile of simms and no clue what it all was 😀
Your comments have been really helpful so far, but now I have stumbled upon two simms which I find hard to 'explain'.
Hope someone can help me here! (I thought I understood, but now I feel kinda lost again haha)

These are the simms:

At first I thought it was a matching pair, but after I had taken the picture, I could clearly tell they are different.

Let's first discuss the left one:

This one has 4MB written on it, no clue whether that is correct or not.

It has six dram chips in total:
3* TM5117200SJ-6
and 3* TM5117200HJ-6

I have struggled to find datasheets for these and I have failed to find one.
But even without those, it does not add up to me.. whether I would devide 4MB by 6 (no parity), or 5 (parity), in my eyes it would all add up to a weird chipsize.
...unless the HJ and SJ differ in size, but that would leave me even more confused I think haha.

The second one:

This one has a handwritten sticker on the back reading 4MB, again, no clue whether correct or not.

This one has 6* TM5117200SJ-6 on them. Also here I do not understand how these add up to 4 MB, or anything?
Also, these 6chips are not really identical. When you look closer, you see 3* the 9642Y version and 3* 9714Y.

Long story short: I feel really confused! haha..

Hope someone can help me understand? Thanks in advance!

They are identical. the SJ and HJ difference, while the datasheet is elusive, could just be a small revision difference.
the other numbers, 9642Y and 9714Y are the manufacturing date codes, 1996 42nd week and 1997 14th week.

Thanks Weedeewee!
Ok, got that cleared out.. Little bit less puzzled 😉

MaTi wrote on 2021-10-21, 13:32:

I ended up on this thread as I had a more or less identical situation; a big pile of simms and no clue what it all was 😀
Your comments have been really helpful so far, but now I have stumbled upon two simms which I find hard to 'explain'.

These modules show all the signs of shady modules: A lot of solder jumpers to "fine-tune" the module, chips you can't find a datasheet for, and in your case, another special bonus: Chips with the same part number having different packages: Some of them are wide SOJ 24/28 (a JEDEC standardized package for early 4Mx4 chips, 2 missing pins in the center on each side) and some of them have wide SOJ 28 (no missing pins). I opened a thread about modules like this at For your amusement: SIMMs with "interesting" design . Your module has the advantage of solder jumpers with labels in the corner: A10 and A11 are two address lines. A10 is only used on 4MB SIMMs, and A11 is only used on 16MB SIMMs. Both jumpers seem to be set to a similar setting, so this likely exposes the address pins of the RAM chips (if present, 4M x 4 chips don't have A11) to the SIMM slot, unlike the first modules in my thread that clamp address bits permanently high or low.

Looking at the solder blobs next to the RAM chips, you will find that exactly 9 blobs are installed - a SIMM (with parity) needs 9 bits. This is no coincidence... On your module, there are 6 x4 chips that provide 24 data bits, and 9 good of them are chosen. On the chips with 4 solder jumpers next to them (one short), only a single bit is used. On the chips with 6 solder jumpers (two short), two bits are used. So I expect the chips on that modules to be broken 4Mx4 chips, downgraded to 4Mx1 and 4Mx2, so the 6 chips yield 4Mx9 in total - at least for the left module. Possibly (the A11 jumpers hints towards it), there were variants of these SIMMs with 16Mx1, 16Mx2 or 16Mx4 chips, but they don't seem standard.