Patching for the Am5x86
Okay, now we need to decide what needs to be changed to support the Am5x86 CPU in the 1995 BIOS.
Because the BIOS_uP_ID is used in multiple places during POST to make decisions depending on the CPU model, the most effective way to add Am5x86 support to a 1995 BIOS is to let the BIOS think it is an Enhanced Am486DX4. Because the 1995 BIOS now uses CPUID for CPU detection, changes have to be made in the CPUID tables, and not in the Reset_ID table.
As we saw in the previous episode about the 1994 BIOS, the Am5x86 can have 4 different Reset_IDs:
0484h: x3 mode and Write-Through cache
0494h: x3 mode and Write-Back cache
04E4h: x4 mode and Write-Through cache
04F4h: x4 mode and Write-Back cache
Note that when using the CPUID instruction, we simply get the Reset_ID on the fly and call it the CPUID Processor Signature, but the value is the same.
The x3 mode CPUID Signatures 048xh and 049xh are also used by the Enhanced Am486DX4 and already supported by the 1995 BIOS, so we only have to add both x4 mode Signatures 04Exh and 04Fxh.
As most 1995 BIOSes now have logic to program the chipset for L1 cache WB automatically, we have to distinguish between L1 cache Write-Through and Write-Back Signatures. So for the Am5x86 we need to have 2 new table items, one with Signature 04E0h (WT) and a second with Signature 04F0h (WB).
Often, there is no room to expand the CPUID Signatures tables at their original location, so we have to copy the AMD signature table to an unused part of the BIOS and add the Am5x86 signatures there.
When using your hexeditor to look for a place to put the expanded table, choose a location before offset E000h that has a continuous block of 00h or FFh bytes. Usually you find this at the end of the code section.
But stay away at least 100 bytes from the last non-zero byte, because the BIOS uses this seemingly empty block to store Power Management data.
Here is an example of a relocated and expanded AMD Signature table placed at offset DD00h, sufficiently away from the end of code.
And this is how the patched AMD Signature table looks like in my disassembler:
So the new AMD table is put at another location and expanded from 4 to 6 items. The 2 added items for the Am5x86 in x4 mode have the same CMOS_3D-uP_ID byte (C5h) as the Enhanced Am486DX4, and the CMOS_3F_data byte for these items has both bits 7 and 6 set to indicate x4 mode. In addition, bit 3 of the CMOS_3F_data byte for signature 04F0h is set to indicate L1 cache WB mode.
This means the following bytes have to be added behind the copied AMD table at the new location:
E0, 04, C5, D0, F0, 04, C5, D8, FF, FF
Then, change the 2 bytes in front of the AuthcAMDenti string to point at the offset of the new table.
In the above example: 1A, 85 -> 00, DD but these values will be different for each BIOS.
Patching for the Cx5x86
To add Cx5x86 x4 mode detection to the 1995 BIOS, we only have to change one 4-byte item in the Cx_DIR0 table. I’ve selected the Cx486S item for that and because this CPU is still detected via the Reset_ID table, we can safely overwrite its item in the Cx_DIR0 table with the required Cx5x86 data.
So this simple patch becomes: 12, 12, 96, 10 -> 2C, 2E, CD, D0
This is how this patch looks in a hexeditor:
The x4 multiplier
What remains is adding x4 multiplier support to the routine that determines the bus_speed (FSB), so the chipset’s DRAM and L2 cache timing registers are programmed correctly.
This fix is the same as for the 1994 Award BIOS, and works now for both the Am5x86 and Cx5x86.
See Part 4 of this story for the details.
Finally, if you had to make changes in the F-segment, remember to correct the last byte of the BIOS to make the checksum good again. 😉
Edit: Around November 1995, Award added Am5x86-P75 and x4 multiplier support to the v4.50G BIOS. So if your socket 3 BIOS is from late 1995/1996, chances are good you don’t need any of the above patches. 😀
In the next part of this story, I will focus on how the compressed Award BIOS can be patched.