carlostex wrote on 2022-05-23, 05:04:

I've been wondering if, one could use something like this to actually lower the final clock of a CPU. Like adding a 2 and 4 divider for the FSB just before the clock hits the CPU. The benefit of this would be to make a Socket 7 CPU much better suited for older games. For instance, setting the FSB on the board to 50Mhz and then setting a divider of 2 between them to lower the clock to 25Mhz. Then a 2x CPU multiplier would give a 50Mhz final CPU speed. This on a Pentium CPU + disabling Brancg prediction and v pipeline would properly give a good match for a 486DX2-66. Taking it further, a divider of 4 would lower the CPU to 25MHz. Lower CPU speeds opposed to just disabling the cache has a smoother slowdown in my experience. Would be nice to have this in a way that 486 speeds would be achievable without the disadvantages of disabling the cache.

It might be possible to use a device like this to disable L2 cache. but the mobo usually has a setting for that.

however, I may have a clock related alternative for you.

Many cyrix chips included a 1x multiplier setting that coincidentally, this tweaker can be used to set on older motherboards.

I'm going to upload a release version of this soon. stay tuned.

Unless anyone has thoughts otherwise, I think I'll leave the holes the same size and just basically make it standard that whomsoever wishes to use this is going to have to solder the pins. because the hole size does look pretty good.

Sphere478 wrote on 2022-05-23, 05:22:

It might be possible to use a device like this to disable L2 cache. but the mobo usually has a setting for that.

however, I may have a clock related alternative for you.

Many cyrix chips included a 1x multiplier setting that coincidentally, this tweaker can be used to set on older motherboards.

None of those solutions is particularly exciting, and i've tried them all. Disabling the L2 can be done in the BIOS and the Cyrix isn't as flexible as the Pentium or specially the Pentium MMX. My idea is about lowering the CPU clock by introducing a divider before the FSB reaches the CPU. This would allow smoother slowdowns without disabling caches. Of course by disabling the caches, lower speeds could be achieved and that is certainly beneficial in some specific cases. But i understand this idea could be difficult to pull off.

I think I have an idea of how to solder these.

Get a paper clip, and some fine solder and make little loops. Cut the loops and put them on each pin, then put some flux down there and hit with hot air?

carlostex wrote on 2022-05-23, 05:42:

Sphere478 wrote on 2022-05-23, 05:22:

It might be possible to use a device like this to disable L2 cache. but the mobo usually has a setting for that.

however, I may have a clock related alternative for you.

Many cyrix chips included a 1x multiplier setting that coincidentally, this tweaker can be used to set on older motherboards.

None of those solutions is particularly exciting, and i've tried them all. Disabling the L2 can be done in the BIOS and the Cyrix isn't as flexible as the Pentium or specially the Pentium MMX. My idea is about lowering the CPU clock by introducing a divider before the FSB reaches the CPU. This would allow smoother slowdowns without disabling caches. Of course by disabling the caches, lower speeds could be achieved and that is certainly beneficial in some specific cases. But i understand this idea could be difficult to pull off.

Honestly, I dont know how you would do it. My device works around programming the internal device that multiplies the bus.

I believe that making it external would possibly have to tap and sever all the bus lines, translate it to a higher clock somehow, then attach to the cpu.

I think it would be a better approach to look into clock gens that support 7mhz fsb

Or just get a mobo that does it.
7mhz fsb details
Lucky Star 5V-1A / 5V-1B review - scaling form XT levels to K6-II levels

Underclocking competition
Socket 5/7 underclock! Aiming for the abyss!

1x multi details
(Solved) Cyrix 400gp/366gp multiplier settings

Behold! Version Pi.0

We're out of beta.

I've tested and checked this prototype as much as I can without actually soldering it on, which I don't think I want to do. (But I can see you definitely need to as there is no connection between the pad and pin without solder according to DVM)

Not much was wrong with it nothing really to report, just a few routing adjustments, Very tiny adjustments.

Minor edit: changed flood clearance. Old clearance was fine though on physical prototype.

Feel free to order and try this one out. 😀

Here is a option that doesn’t solder the processor. 🤔

Gotta cut out the bottom though.

More info on this in the voltage interposer thread.

The fit on these pins is very tight. I should check with a volt meter and see if the pins are connecting.. edit, looks like good press fit. Good connection readings

I set the plated holes on the processor tweaker to 0.020”

I measure the LIF socket pins at 0.021”

So it seems that a 0.001” interference fit works well.

If I recall, the processor pins seem to be 0.017-0.018” so setting it to 0.016 should in theory work.

But does jlcpcb manufacture with such precision? Or will they just use a 0.020 drill bit?

Sphere478 wrote on 2022-05-23, 06:32:

I believe that making it external would possibly have to tap and sever all the bus lines, translate it to a higher clock somehow, then attach to the cpu.

My hipothetical idea is to divide the clock just before it touches the CPU. Dividing the 50MHz bus, let's say by 2, before the CPU and send it to the CLK pin while using a 2x multiplier would yield a 50MHz CPU speed. This would effectively "trick" the CPU into believing the FSB is 25MHz when it is not. The benefits are obvious: you only slow down code execution by halving the clock speed and keep bus access effectively the same. This leads to excellent system responsiveness while only slowing the code execution.

I think it would be a better approach to look into clock gens that support 7mhz fsb

By my own experience i have to strongly disagree. I have a DFI 586 ITOX motherboard using a ICS9169 PLL with the ability to clock at 7Mhz. The experience sucks completely. The code execution of the CPU is fine at 14Mhz, its as fast as a low clocked 486 but the I/O and the system responsiveness gives an experience far slower than an IBM PCjr. A cold boot is excrutiatingly slow, imagine Pentium boot code having to run with such crippled I/O and memory access.

Also look above: So BUS clock is 7,159MHz and PCI clock is divided by 4! So instead of a 25Mhz PCI bus clock when selecting a 50MHz FSB you get 3,57MHz for the PCI clk. That's astonishing slow and not helpful at all. Plus USB ports will stop working and everything on the Super I/O that requires the 24MHz clock to work will stop working, including the keyboard. To try out this setting, i had to sever the CLK trace going to super I/O and then mod a 24MHz TTL oscillatopr and patch into it. Only then i could do anything useful. Still, the system is just not useful that way, Disk I/O, Memory I/O and Video are extremely slow rendering the system a complete useless thing. Its fun to try it once, but not useful at all.

I'm not saying that what i'm suggesting is easy in any way, and i understand its completely out of scope for this project but it's just an idea. Thoretically a Pentium or Pentium MMX at 50MHz would be as fast as a 486DX-100WB, but disabling branch prediction, V pipe and MB cache could bring it down quite a bit into mid 486 levels.

Is the CLK input on the CPU just a TTL signal? If it is i wonder if i could feed the a CPU clock directly.

carlostex wrote on 2022-05-24, 01:59:

My hipothetical idea is to divide the clock just before it touches the CPU. Dividing the 50MHz bus, let's say by 2, before the C […]
Show full quote

Sphere478 wrote on 2022-05-23, 06:32:

I believe that making it external would possibly have to tap and sever all the bus lines, translate it to a higher clock somehow, then attach to the cpu.

My hipothetical idea is to divide the clock just before it touches the CPU. Dividing the 50MHz bus, let's say by 2, before the CPU and send it to the CLK pin while using a 2x multiplier would yield a 50MHz CPU speed. This would effectively "trick" the CPU into believing the FSB is 25MHz when it is not. The benefits are obvious: you only slow down code execution by halving the clock speed and keep bus access effectively the same. This leads to excellent system responsiveness while only slowing the code execution.

I think it would be a better approach to look into clock gens that support 7mhz fsb

By my own experience i have to strongly disagree. I have a DFI 586 ITOX motherboard using a ICS9169 PLL with the ability to clock at 7Mhz. The experience sucks completely. The code execution of the CPU is fine at 14Mhz, its as fast as a low clocked 486 but the I/O and the system responsiveness gives an experience far slower than an IBM PCjr. A cold boot is excrutiatingly slow, imagine Pentium boot code having to run with such crippled I/O and memory access.

Also look above: So BUS clock is 7,159MHz and PCI clock is divided by 4! So instead of a 25Mhz PCI bus clock when selecting a 50MHz FSB you get 3,57MHz for the PCI clk. That's astonishing slow and not helpful at all. Plus USB ports will stop working and everything on the Super I/O that requires the 24MHz clock to work will stop working, including the keyboard. To try out this setting, i had to sever the CLK trace going to super I/O and then mod a 24MHz TTL oscillatopr and patch into it. Only then i could do anything useful. Still, the system is just not useful that way, Disk I/O, Memory I/O and Video are extremely slow rendering the system a complete useless thing. Its fun to try it once, but not useful at all.

I'm not saying that what i'm suggesting is easy in any way, and i understand its completely out of scope for this project but it's just an idea. Thoretically a Pentium or Pentium MMX at 50MHz would be as fast as a 486DX-100WB, but disabling branch prediction, V pipe and MB cache could bring it down quite a bit into mid 486 levels.

Is the CLK input on the CPU just a TTL signal? If it is i wonder if i could feed the a CPU clock directly.

Do you have a schematic and a IC in mind?

If so we could maybe do a collaborative effort.

But I think if the bus and clock are out of sync that it would cause a error would it not?

If you are right though and you just have to change the clock pin…. Omg.. woupdn’t that just be amazing because that also opens up higher clocks also.

In any case, I think if you feel that there is something to this that we should make a new thread.

I’ll make it if I am to do the pcb part of it so I can keep OP updated with progress. But let me know your thoughts.

Edit: Socket 5/7/SS7 (clock signal interposer) Tweaker (Research)

Socket 5/7/SS7 (Processor interposer) Tweaker (canceled: superseded/merged by Voltage Interceptor)

new solderless project that incorporates heatsink clips

Awesome work - props!

Thanks 😀

Regarding press fit:
As far as I understand the thread currently the CPU pins just about clear the shim PCB holes with very little wiggle room.
Would it be possible to hack/convert this into press fit by soldering the holes shut first and revoving (most of) the solder from the holes with a solder sucker in a second step? This would leave behind a thin coating of relatively soft solder inside the holes that may just be enough to tightly bridge the gap between hole and pin and create a makeshift press fit solution.

Doornkaat wrote on 2022-05-28, 07:59:

Regarding press fit:
As far as I understand the thread currently the CPU pins just about clear the shim PCB holes with very little wiggle room.
Would it be possible to hack/convert this into press fit by soldering the holes shut first and revoving (most of) the solder from the holes with a solder sucker in a second step? This would leave behind a thin coating of relatively soft solder inside the holes that may just be enough to tightly bridge the gap between hole and pin and create a makeshift press fit solution.

I had that thought also.

It might work.

Yeah it’s a pretty good fit as is. A few thousands of a inch smaller and it might press fit.

But as it is now it does not press fit the connections are no good. They must be soldered. Adding solder may make it work.

I can whip up a 0.016” hole variant if you wanna prototype a press fit beta? 😀

What I don’t know though is if jlcpcb will actually make the holes that size or if they just use standard drill bit sizes. We would have to ask or try and find out.

I may be able to test the solder idea when I get my hot air station fixed.

Sphere478 wrote on 2022-05-28, 08:08:

I has that thought also. […]
Show full quote

Doornkaat wrote on 2022-05-28, 07:59:

Regarding press fit:
As far as I understand the thread currently the CPU pins just about clear the shim PCB holes with very little wiggle room.
Would it be possible to hack/convert this into press fit by soldering the holes shut first and revoving (most of) the solder from the holes with a solder sucker in a second step? This would leave behind a thin coating of relatively soft solder inside the holes that may just be enough to tightly bridge the gap between hole and pin and create a makeshift press fit solution.

I has that thought also.

It might work.

Yeah it’s a pretty good fit as is. A few thousands of a inch smaller and it might press fit.

But as it is now it does not press fit the connections are no good. They must be soldered. Adding solder may make it work.

I can whip up a 0.016” hole variant if you wanna prototype a press fit beta? 😀

What I don’t know though is if jlcpcb will actually make the holes that size or if they just use standard drill bit sizes. We would have to ask or try and find out

Have you tried bridging the gap with solder on the 0.02" hole diameter prototypes you currently have?
I'd like to offer help testing the prototype shims with reduced hole diameter but currently I don't have any S5/7 stuff at hand as I'm taking a break from messing with retro hardware. The hobby was interfering with real life tasks too much. 😐 I put everything into storage a few towns over.
If it can wait hit me up again in August. I hope to have gotten things back on track by then.

Doornkaat wrote on 2022-05-28, 08:19:

Have you tried bridging the gap with solder on the 0.02" hole diameter prototypes you currently have? I'd like to offer help tes […]
Show full quote

Sphere478 wrote on 2022-05-28, 08:08:

I has that thought also. […]
Show full quote

Doornkaat wrote on 2022-05-28, 07:59:

Regarding press fit:
As far as I understand the thread currently the CPU pins just about clear the shim PCB holes with very little wiggle room.
Would it be possible to hack/convert this into press fit by soldering the holes shut first and revoving (most of) the solder from the holes with a solder sucker in a second step? This would leave behind a thin coating of relatively soft solder inside the holes that may just be enough to tightly bridge the gap between hole and pin and create a makeshift press fit solution.

I has that thought also.

It might work.

Yeah it’s a pretty good fit as is. A few thousands of a inch smaller and it might press fit.

But as it is now it does not press fit the connections are no good. They must be soldered. Adding solder may make it work.

I can whip up a 0.016” hole variant if you wanna prototype a press fit beta? 😀

What I don’t know though is if jlcpcb will actually make the holes that size or if they just use standard drill bit sizes. We would have to ask or try and find out

Have you tried bridging the gap with solder on the 0.02" hole diameter prototypes you currently have?
I'd like to offer help testing the prototype shims with reduced hole diameter but currently I don't have any S5/7 stuff at hand as I'm taking a break from messing with retro hardware. The hobby was interfering with real life tasks too much. 😐 I put everything into storage a few towns over.
If it can wait hit me up again in August. I hope to have gotten things back on track by then.

Missed a edit: yeah, I can try that out but it may have to will wait until I fix my hot air station,

Eh, I guess maybe I can get it done with a iron.. will try and check that out when I get time.

Sphere478 wrote on 2022-05-28, 08:23:

Doornkaat wrote on 2022-05-28, 08:19:

Have you tried bridging the gap with solder on the 0.02" hole diameter prototypes you currently have? I'd like to offer help tes […]
Show full quote

Sphere478 wrote on 2022-05-28, 08:08:

I has that thought also. […]
Show full quote

I has that thought also.

It might work.

Yeah it’s a pretty good fit as is. A few thousands of a inch smaller and it might press fit.

But as it is now it does not press fit the connections are no good. They must be soldered. Adding solder may make it work.

I can whip up a 0.016” hole variant if you wanna prototype a press fit beta? 😀

What I don’t know though is if jlcpcb will actually make the holes that size or if they just use standard drill bit sizes. We would have to ask or try and find out

Have you tried bridging the gap with solder on the 0.02" hole diameter prototypes you currently have?
I'd like to offer help testing the prototype shims with reduced hole diameter but currently I don't have any S5/7 stuff at hand as I'm taking a break from messing with retro hardware. The hobby was interfering with real life tasks too much. 😐 I put everything into storage a few towns over.
If it can wait hit me up again in August. I hope to have gotten things back on track by then.

Missed a edit: yeah, I can try that out but it may have to will wait until I fix my hot air station,

Eh, I guess maybe I can get it done with a iron.. will try and check that out when I get time.

Suboptimal tools may be better for this job; it has to be a bit messy to work.😄

Here is a adjustment to see if we can get the press fit working. Recommend the pi.0 version until this one passes prototype. Holes may be too small on pi.01.

Set blank holes to 0.020", set conductive holes to 0.016"

Anyone wanna have a try at it?

Latest prototype arrived!

Latest gerber as posted above download/file.php?id=138425

0.016” didn’t work. I have connection on about half of the pins.

Try for 0.015”? Or admit defeat and just solder them? 🤔

Pushing the shim on was a pretty snug fit. Hard to say for sure if holes are smaller though.

As of now, the design seems fine, you’ll just have to plan on soldering it though.

Make little rings out of super thin solder push them down the pins and put some flux there and hit it with hot air.

I am very curious as to how this could be made Tillamook only and soldered to the top of the chip - as a rather more "professional"\neater solution than having bodge wires on the top of the CPU to get them working properly on a desktop motherboard...

I have a whole bunch of Tillamooks arriving soon, (all of them will be SL2Z4, 266MHZ, Socket 7, but low voltage) some of which will go into suitable PCs and may end up staying there... so a nice manufactured PCB may well be quite the talking point in another 20 years time!

As an aside - Also I'd love to know what software you have used to design these - as my version (latest) of PCB Wizard hasn't been updated since 2009... so it might be time for me to move over to something more modern!