VOGONS


First post, by PlaneVuki

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Hi.

Is there a way or a hack to force x1 multiplier on socket5/7 so to run p1 at 50-60-66mhz?

As far as I know most, if not all, start from x1.5.

Thanks in advancee.

Reply 1 of 13, by zyga64

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Intel Pentium minimum multiplier is 1.5x, but you can force 1x for Cyrix 6x86 (non MX) - set it for 2.5x.
https://www.pchardwarelinks.com/cpuspeed.htm

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Reply 2 of 13, by Sphere478

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Pentium p54c overdrive with tape over the pad for the fan sensor might do it…?

Re: Socket 5 / 7 Pentium Overdrives. Higher Multipliers? SMP? Let’s find out..

But yes, some cyrix chips do have a 1x multi. MII had this feature until the 2.2v cores.

Re: Cyrix 400gp multiplier settings

Last edited by Sphere478 on 2022-09-27, 14:06. Edited 2 times in total.

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 3 of 13, by BitWrangler

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Also you can check for undocumented clock chip "FSB" settings, some of them might do 486 clocks, like 33 or 40 Mhz, so you can set that at 1.5x to get it slower. One board that can really slam the brakes on is this one.. Lucky Star 5V-1A / 5V-1B review - scaling form XT levels to K6-II levels

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 5 of 13, by dionb

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Quite a few So4 boards have 50MHz FSB stetings. As those CPUs (P60/P66) have 1x multiplier it's pretty easy to get 1x50MHz with them.

PlaneVuki wrote on 2022-09-27, 15:32:

No tricks like putting tape on regular pentium pin?

No. The mapping is hardcoded. So5 has a single pin/bit (BF0) to switch between 1.5x and 2.0x, So7 has two (BF0 and BF1) to switch between those two and 2.5x and 3.0x as well. In P55C (Pentium MMX) the 1.5x is remapped to 3.5x.

Reply 6 of 13, by Sphere478

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PlaneVuki wrote on 2022-09-27, 15:32:

No tricks like putting tape on regular pentium pin?

To the best of my knowledge the lowest multi on pentium socket 5/7 is the 1x of a pentium overdrive with a bad fan. Though I don’t have a non mmx overdrive for socket 5 to verify this.

In my tests, it didn’t seem to work on pentium mmx overdrive though. (Though they would slow down by some other means, possibly cache?) Past that, non mmx chips go as low as 1.5x and mmx chips go as low as 2x

There isn’t a pin trick to get around this

As said above socket 4 pentiums had 1x and socket 3 overdrives had 1x with the fan off.

Last edited by Sphere478 on 2022-09-27, 17:21. Edited 2 times in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 7 of 13, by BitWrangler

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From early datasheets ~1994, it looked like the early early 1st gen (Likely gold cap P75, P90 with fdiv bug) socket 5 could maybe be forced into a 1x mode. I think at that point they weren't sure if they were gonna manage to keep them sync with bus like socket 4. But then the BF1 pin was defined in next revision and 99.5% of the CPU out there are gonna be 1.5/2.0 switchable. That's what you'll find in 96-98 datasheets.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 8 of 13, by Anonymous Coward

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Podp5v83 does 1x when the fan is bad, but podp5v133 does not. I’ve never tried socket5 overdrives, but unless you can confirm the function of the fan pins I wouldn’t assume they behave the way you want.

"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium

Reply 9 of 13, by melbar

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dionb wrote on 2022-09-27, 15:33:

No. The mapping is hardcoded. So5 has a single pin/bit (BF0) to switch between 1.5x and 2.0x, So7 has two (BF0 and BF1) to switch between those two and 2.5x and 3.0x as well. In P55C (Pentium MMX) the 1.5x is remapped to 3.5x.

zyga64 wrote on 2022-09-27, 12:24:

Here in these charts, Socket 5 is related to 1x and 2x only.

Well, this is strange: I have a socket 5 board (SI54P AIO, Revision V2.)
Today, there is a P75 installed.
I have stored both manuals of SI54P AIO, Revision 1.0 and 2.0.

According to this socket 5 board, Rev. 1.0 , a pentium 100 Mhz is max. possible to install.
According to this socket 5 board, Rev. 2.0 , a pentium 150 Mhz is max. possible to install. (But cpu clock select and internal clock is written: 66Mhz [JP7] , 2.5X external clock [JP17])

Is the difference to selected chipset the reason, that my socket 5 board is an "effective" socket 7 board?

Chipset of SI54P AIO, Revision 1.0: SiS 85C501, SiS 85C502, SiS 85C503).
Chipset of SI54P AIO, Revision 1.0: SiS 5501, SiS 5502, SiS 85C503).

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Reply 10 of 13, by Sphere478

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The multiplier is in the cpu. Not in the socket/mobo

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 12 of 13, by dionb

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melbar wrote on 2022-10-01, 10:56:
dionb wrote on 2022-09-27, 15:33:

No. The mapping is hardcoded. So5 has a single pin/bit (BF0) to switch between 1.5x and 2.0x, So7 has two (BF0 and BF1) to switch between those two and 2.5x and 3.0x as well. In P55C (Pentium MMX) the 1.5x is remapped to 3.5x.

zyga64 wrote on 2022-09-27, 12:24:

Here in these charts, Socket 5 is related to 1x and 2x only.

Incorrect, So 5 is 1.5 and 2x, not 1x and 2x.

Well, this is strange: I have a socket 5 board (SI54P AIO, Revision V2.) Today, there is a P75 installed. I have stored both […]
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Well, this is strange: I have a socket 5 board (SI54P AIO, Revision V2.)
Today, there is a P75 installed.
I have stored both manuals of SI54P AIO, Revision 1.0 and 2.0.

According to this socket 5 board, Rev. 1.0 , a pentium 100 Mhz is max. possible to install.
According to this socket 5 board, Rev. 2.0 , a pentium 150 Mhz is max. possible to install. (But cpu clock select and internal clock is written: 66Mhz [JP7] , 2.5X external clock [JP17])

Is the difference to selected chipset the reason, that my socket 5 board is an "effective" socket 7 board?

Rev 1.0 doesn't seem to have any multiplier jumper, so no way of influencing BF0 pin on the CPU - effectively hard-coding it to 1.5x multiplier.
Rev2.0 has two multiplier jumpers to set BF0 and BF1. That makes it de-facto So7. The Pentium 150 is a Socket 7 CPU.

More interesting question is why it claims to support up to 150MHz only when the jumpers present allow selecting up to 200MHz. This could simply be because at time of release of the board (or its manual!) the P150 was the newest CPU. But... the P150 was released on January 4th 1996, and the P166 was released on the same day. So there was never a time with P150 but without P166. That means there could be another reason, most likely the capacity of the VRM to supply 3.3V to the CPU from the 5V line. The highest power draw by a supported CPU is the 12.81W by the P120 (slightly more than P133 or P150), the P166 needs 14.5W. So that might be more than ECS was happy to recommend on this board.

Reply 13 of 13, by Anonymous Coward

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It could also be that the designers of the board speculated or had heard rumours of the P150s release, and prematurely added it to the list of supported CPUs.

"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium