Perhaps if you use slower 70 ns FPM memory, the L2 would yield some improvement.

Marco wrote on 2023-01-20, 13:33:

Off topic:
I also owned the P54TP4 back in the days with 512kb non PB cache plus EDO. and all benches were indeed faster with L2 disabled. Especially when running bus at 80MHz. Never understood why.

Anyway fantastic engineering here so far. Good luck with the new board.

Meant to say 80MHz meaning PCI is now 40MHz and FSB is 80MHz, that's overclocking?

Cheers,

Indeed yes. Nice evening

Marco wrote on 2023-01-20, 22:29:

Indeed yes. Nice evening

Thank you for clarifying. That's impressive given the FX chipset is good to 75MHz most of time. I think you might be running at 83MHz?

Cheers,

Nope. It was indeed 80MHz. My Pentium 100 ran at 80x1,5=120MHz. Maybe 40x3 better said. My successor board the P55Tp4 could run at 83.

See also here:
ASUS PCI/I-P54TP4 Socket 5 motherboard thread/review

Today I upgraded a Jetway "J-656B" Intel FX mainboard from asynchroneous DIL-SRAM to 512K PB-SRAM.
https://theretroweb.com/motherboards/s/jetway-j-656b

Similar to the Asus case here I first removed the DIL chips desoldered the two octal latch circuits (U24, U25) and equipped the board with 2 x 64K x 32 PB chips. I also had to upgrade the TAG chip from 8K x 8 to 32K x 8.
Before that I had already populated the VRM connector to be able to use split voltage CPUs.

To my surprise only 256K L2 cache were detected - correctly as "SRAM Type: Pipeline". The memory performance increased significantly.
I measured all the address-, I/O and TAG-I/O lines and found that there was no connection between the pins 49 (A16) of the the cache chips. There was also no connection between these two and pin 49 (HA18) of the TSC.
So I established this connection with some wire and now all 512K L2 cache are detected and can be used.

Besides changing jumper "JP14" from 256K to 512K there was no need for adjusting / adding any strapping resistors or jumpers. Everything is auto-detected an configured by BIOS.
The triple-jumper-blocks JP1 and JP2 are for selecting the voltage (3.3 / 5V) of the DIL-chips ONLY.

The motivation for doing this "mod" was the annoying instability of this mainboard with Pentium-S CPUs like the SY045 (non-split-voltage) when 8 DIL chips were present.
There are just 2 electrolytics for buffering the 3.3 / 3.4 V rail for CPU core, I/O and everything else, so obviously heavier loads cause transients and lock up the system. The J-656B seemt to be a true cheapo-design.
The two PB-SRAM chips consume less energy and they are located beside the CPU.
Other 430FX mainboards have a dozen or more 470µF electrolytics for buffering.