These blurry pics can trick you - everything is possible.
Just try it, cut the trace...

You can also check if the new chips have all the "chip enable" etc. pins at the right level.

I already gave you that information 😀

>CACHE CONTROL REGISTER
>Address Offset: 52h
5:4 SRAM Type (SRAMT): This field reflects the inverted signal level on the A[29:28] pins at the rising
edge of the RESET signal (default). The default values can be overwritten with subsequent writes to
the CC Register. The options for this field are:
Bits[5:4] SRAMType
0 0 Pipelined Burst
0 1 Burst
1 0 Asynchronous
1 1 Pipelined Burst for 512K/Dual-bank inplementations. Selects 3-1-1-1-2-1-1-1 instead of
3-1-1-1-1-1-1-1 back-to-back burst timings with NA# enabled. An extra clock is inserted
for bank turnaround. SGS must be set to 10.

> After a hard reset, CC[7:4] reflect the inverted signal levels on the host address lines A[31 :28].

its no TCS Address pins, can also be changed live? try DEBUG.exe
o CFB 52
i CFC

Looks like the ASUS BIOS (302) has no entry for register 52h

CTCHIP34 has access to the Triton registers. I'll see what it shows as being setup, then modify 52h. I won't be able to check until late this evening.

It seems odd that BIOS v302 wouldn't have 52h. There is also a v103. Would Async SRAM work if 52h left blank?

I've a strong feeling that the NA jumper's trace needs to be cut, but I'll trace the traces prior. i've seen some PCB manufacturers from the mid-90's employ as part of their jumper settings, to "cut trace at jumper block X", e.g. the Transcomputer module.

>CACHE CONTROL REGISTER
>Address Offset: 52h
>Access: SSSS0010 (S = Strapping option)
> After a hard reset, CC[7:4] reflect the inverted signal levels on the host address lines A[31 :28].

Seems to be the same as HX chipset.
Here are the signal levels:

and the register values

The good thing is, the voltages can be measured at the FX northbridge easily.

rasz_pl wrote on 2022-11-17, 17:54:

>CACHE CONTROL REGISTER >Address Offset: 52h >Access: SSSS0010 (S = Strapping option) > After a hard reset, CC[7:4] reflect the […]
Show full quote

>CACHE CONTROL REGISTER
>Address Offset: 52h
>Access: SSSS0010 (S = Strapping option)
> After a hard reset, CC[7:4] reflect the inverted signal levels on the host address lines A[31 :28].

Sorry, I thought I was clear earlier. I am intending to use CTCHIP34 to read 52h, that is CC[7:4] after a hard reset. Determine which bit 7 thru 4 isn't set correctly, then find where A28-A31 go, presumably to those unpopulated jumpers.I also will see if CHCHIP34 is able to adjust those bits and see if L2 works on the fly like this.

Or were you suggesting another course of action?

majestyk , this is the chart you're looking for, 430FX. You chart has 'reserved' where it shouldn't be. I just need to remember that the signals are inverted.

I still find the shorting of the NA jumper suspicious.

feipoa wrote on 2022-11-17, 18:30:

Sorry, I thought I was clear earlier. I am intending to use CTCHIP34 to read 52h, that is CC[7:4] after a hard reset. Determine which bit 7 thru 4 isn't set correctly, then find where A28-A31 go, presumably to those unpopulated jumpers.I also will see if CHCHIP34 is able to adjust those bits and see if L2 works on the fly like this.

Or were you suggesting another course of action?

I understood "Would Async SRAM work if 52h left blank?" differently 😀 as 52h clearly is not blank

"Reserved" since HX didn´t support async. anymore...
But the "inversion logic" is the same.

Does your ctchip34 support this chipset? Mine has configs for all kinds of chipsets but I cannot find Intel.

majestyk wrote on 2022-11-17, 19:05:

"Reserved" since HX didn´t support async. anymore...
But the "inversion logic" is the same.

Does your ctchip34 support this chipset? Mine has configs for all kinds of chipsets but I cannot find Intel.

Yes, look into INTELPCI.CFG. Has support for Triton and, more specifically, 52h is listed with the option shown from the datasheet I posted.

majestyk, I'm starting to wonder if that photo you found of the P54TP4 w/PB SRAM is correct. Is that a stock image from Asus? Where did you find it? When I look at the traces, I see traces going between the TAG chip and the 74F245 chip, as well as traces going from the 74F245 chip to the PB SRAM chip. Should I solder them back on?

After I ran CTCHIP34, I see the settings for 52h are: 0010XX11. I think they are supposed to be: 0100XX01. When I force this setting, CTCHIP hangs.

I cut the NA#, or JP15 trace, however screen stays blank with it cut. I then soldered on the remaining jumpers, JP13-JP15, as well as four 0805 SMD 4.7 K-ohm resistors. Two are pull-up to 3.5 V, while the other two are pull-down to GND.

I set the jumpers on JP13: 1-2, JP14: 1-2, which should equate to 256K SRAM, but CTCHIP still shows L2 disabled. I tried JP13 and JP14 on 2-3, but CTCHIP still showed L2 disabled.

The pinouts for the jumper block is shown below. Unfortunately, there is nothing that goes to A29 or A28, which would set the SRAM type to Pipeline Burst. CTCHIP34 shows the SRAM type as Async.

I traced out chipset pins A29 and A30, but they only go directly to the CPU's A29 and A30. I couldn't find a jumper block where they locate.

I figured that maybe these settings needed to be available before POST, so I modified the BIOS to include a chipset register 52h. Both the v302 and v103 variants of this BIOS do not have register 52h in the BIOS.

I tried one BIOS with 52h as 01000001, and another with 0100XX01. Unfortunately, the monitor stayed blank at power-up. Maybe I got the setting wrong? Or maybe the 245 transceiver chips are needed for use with the TAG RAM?

I think you should put the TX back

I can´t remember where I found the pic, but it´s not very likely someone pillaged the transceivers.

First guess: There might have been two different BIOSes for the two versions, the PBurst version would be hard to find today since there were not many boards made this way. But I doubt that, ASUS integrated as many options as possible into the BIOS for one model to keep things simple.

Have you checked if the connections on the pin 1-10 side of the transceiver chips reach the two QFP100 Intel-tranceivers / buffers or the northbridge? The ones at the pin11-20 side go to the DIL sockets, each line to 4 of them. These are the address lines.

feipoa wrote on 2022-11-18, 14:18:

When I look at the traces, I see traces going between the TAG chip and the 74F245 chip, as well as traces going from the 74F245 chip to the PB SRAM chip. Should I solder them back on?

where do TAG ram data pins route? only to the buffer? then maybe yes, but there needs to be a mechanism that only enables buffers when accessing TAG ram, otherwise they would be enabled when reading from SRAM and would override data with garbage

feipoa wrote on 2022-11-18, 14:18:

After I ran CTCHIP34, I see the settings for 52h are: 0010XX11. I think they are supposed to be: 0100XX01. When I force this setting, CTCHIP hangs.

either its impossible to change cache type on live system without additional precautions like manual cache flush or you are right about the TAG

feipoa wrote on 2022-11-18, 14:18:

I cut the NA#

I didnt see anything about cutting NA# in the datasheet
> NA# on the TSC must be connected to the CPU NA# pin for all configurations.

feipoa wrote on 2022-11-18, 14:18:

The pinouts for the jumper block is shown below. Unfortunately, there is nothing that goes to A29 or A28, which would set the SRAM type to Pipeline Burst.
I traced out chipset pins A29 and A30, but they only go directly to the CPU's A29 and A30. I couldn't find a jumper block where they locate.

"JP12 pulls down A[31:30]", there definitely should be connection thru aa resistor.
how to find: https://www.youtube.com/watch?v=ehyfmMw29NU

Thanks for your comments. What I thought and hoped would be a quick upgrade has become more involved.

To clarify, NA# is JP15. There's a trace connecting the two pins of JP15. I cut the trace and put a jumper in place. I found it odd that Asus had a jumper shorted, so figured it was worth a try. I could solder the trace back together, but I am OK to leave the jumper shorting JP15.

Why do you say JP12 pulls down A[31:30]? It is JP13 and JP14 which either pulls A31/A30 up or down. JP12 may be irrelevent to using PB SRAM.

The possibility of the disallowed live-stream alteration of A[28:31] with CTCHIP34 shouldn't matter because I also provided two hard-coded BIOS options. I wrote to EEPROMs and tested. It is possible that there's more to it than just adding these settings in Awdbedit/MODBIN. Thus, I will try borrowing other 430FX BIOSes. I have a PC Chips board that I first tested these SRAM modules in to ensure they were working. I will try that PC CHIPS BIOS.

Does anyone have the 'Full Yes 82430I' BIOS? EDIT: Many are here, https://theretroweb.com/motherboards/s/full-y … 430fx#downloads , but if you have one you copied personally, I'd try that first.

I also find it unlikely that Asus made two different BIOSes for PB and ASYNC SRAM. I will look into where the transceiver and TAG traces go after first testing the PC CHIPS BIOS.

In looking at an image of the Full Yes Intel 82430FX board with PBSRAM present and ASYNC removed, I don't see anything that looks like unpopulated 245 transceiver pads. On the contrary, I see what looks like two DIP 245 chips. However, I cannot read the part number.

I tried the FULL YES motherboard's v3.41 BIOS on the ASUS board, but the screen stays blank. POST card's last message is 07, which the booklet states as "Verifies CMOS is working correctly, detects bad battery". I noticed the FULL YES board uses a different RTC module compared to the ASUS board - FULL YES has a VIA RTC while Asus has Dallas RTC. I'm not sure if this is related to the no-POST.

rasz_pl wrote on 2022-11-18, 15:50:

where do TAG ram data pins route? only to the buffer? then maybe yes, but there needs to be a mechanism that only enables buffers when accessing TAG ram, otherwise they would be enabled when reading from SRAM and would override data with garbage

Just looked at the image of the motherboard I uploaded previously, download/file.php?id=150310&mode=view , I see traces going from TAG to the 74F245 and SRAM in parallel. Should I map them all out, or just put the 74F245 buffers back for another test?

Brainstorming:

- the silkscreen inside the QFP-100 pads say "burst SRAM", so perhaps I need to set the RAM into burst mode rather than pipelined burst mode. I should mod my BIOS for this option and try again.

- there were different revisions of the 430FX chipset. My Asus board uses SZ966, however my PCCHIPS board uses SZ999.

- PC CHIPS 430FX board doesn't have any 245 chips on it, nor does the COAST module. Implies 245's on the Asus board not necessary

- Maybe there really was a particular Asus BIOS version for the PBSRAM variant of this board, it just never showed up online because that variant had no updates provided.

- It would be nice to know where JP35 on the FULL YES motherboard goes. Anyone know who youtuber vswitchzero is on the forums?