Hi mbarszcz,

I believe you missed a few jumper settings. 😉
The L1 cache WB mode of Intel and AMD 486 CPUs is controlled by jumpers and not by the BIOS.
The L1 cache WT/WB option in the BIOS is controlling the chipset and for software control of WB mode on Cyrix CPUs.

For an Intel 486DX4 WB, you have to use the P24D jumpers for CPU Type Selection:

JP27: 1-2, 3-4
JP28: 1-2, 4-5
JP29: 1-2, 4-5
JP30: 3-4, 5-6
JP32: 1-2
JP33: 1-2, 3-4

The other jumper settings should remain the same as for a DX4-100, so 3.3V Vcore, 33MHz FSB and x3 multiplier.
With the above settings, and a CPU that supports WB, the CPU should operate in L1 cache WB mode and my CHKCPU tool should clearly tell you so. 😀

Then of course you need to run a BIOS that support this, like the AMI 1995X or the patched Award M912_J2 BIOS from Re: PC Chips M912 BIOS update for Am5x86 and Cyrix 5x86

Please let us know if this works.
Jan

Hi Jan, Thanks for making the CHKCPU utility 😀 I am running the AMI 1995X BIOS (the board came with the original 1994 bios ROM.

I would have never in a million years guessed that those would have been the right jumper settings to pick, but you were right. After setting them, ckhcpu now shows the correct CPU and WB mode just like you said. How is it that chkcpu actually shows a different CPU-ID when the jumpers are in the wrong position? I would have thought that it would have read that off the chip just the same. With the jumpers in the wrong position, I believe it showed as 0483 before (or 0480, can't quite remember, but it definitely wasn't 0490 before).

Unforunately even with it showing up correctly in write-back mode there is still the same same strange behavior though when the bios is set to write-back mode.

You mentioned that the jumpers control the CPU and the BIOS controls the chipset/software control. Somehow the chipset setting seems to still be messing things up. Even with the jumpers in the correct position, having write-back enabled in the bios causes Chris's 3D benchmark to run really slow (7.6fps instead of 48fps), and cachechk to report the following error "It looks like megabyte #1 isn't being cached".

Speedsys also shows steady slow write throughput performance with no cache "steps" in the graph.

Setting the bios to write-thru causes the system to work normally again (and ckhcpu still reports it being in write-back mode), but it still doesn't appear to actually be using write-back mode, unless I just don't know what I'm looking for 🤔 (wihch is also a very real possibility).

Okay, you got the CPU in L1 cache WB mode, great! 😀

Yes, it is true that Write-Back capable Intel and AMD 486 CPUs will change their CPUID Signature depending on the L1 cache mode. CHKCPU knows these CPUID values and translates them in readable English for the L1 cache mode display.
Note that Cyrix 486/5x86 CPUs don’t support CPUID, but these CPUs have another mechanism to report the WB mode so CHKCPU can display this info on Cyrix CPUs as well.

This AMI BIOS behavior on Internal cache Wr-Back option is strange indeed.
Can other M912 users chime in here to confirm this BIOS behavior?

I’m unfamiliar with the inner workings of the AMI WinBIOS, but on the Award BIOS for the UMC498 chipset I know that this option is functional on Cyrix CPUs only and is used to program the Cyrix CPU for WB mode.

I know from other 486 chipsets that the BIOS also needs to control specific chipset registers to enable L1 cache WB mode, but I never found this logic in BIOSes for UMC498. I assume the UMC498 doesn’t need this programming and is always “on” to receive signals from a WB capable CPU, but because datasheets for UMC498 are nowhere to be found, this is just a guess.

When using the AMI BIOS, just keep the Internal cache option on Wr-through for now.
You can test the correct functioning of the L1 cache WB mode by booting from a DOS 6.x floppy. If you don’t get a hang here, the chipset/CPU interface for L1 cache WB mode works correctly.

Merry Christmas,
Jan

Weren’t there wb and non wb versions of the dx4? How do you tell from the markings?

Sphere478 wrote on 2022-12-25, 01:39:

Weren’t there wb and non wb versions of the dx4? How do you tell from the markings?

The &EW on the chip is supposed to indicate writeback, &E means write through.

Gotcha. Thx

On AMD it's the difference between V8T, NV8T (WT) and SV8B (WB).
Note that the WT 486 from AMD needs to be jumpered like a DX2 (with 3.3 Volt!) and the WB 486 like the Intel DX4 (3.3 Volt too!).