At first I thought of "setmul" but then found this

appiah4 wrote on 2019-06-26, 14:01:

L2 cache is not on the CPU and in many Socket 7 boards cache amount can only be set by jumpers not through BIOS or other CPU registers. In these cases the L2 cache switches are useless. If you use a CPU with onboard L2 cache such as the K6-22+ on these boards the L2 commands will disable the L2 cache but then you'll still have L3 cache in the form of motherboard cache.

If you can get board to a electronics repair and spare donor board, move the ATX connector from donor to Dell board in different location. Dell connector has one missing pin in that connector, hence need for a ATX board donor for ATX connector.

I repeat, do not attempt to power up using ATX till you do this modification or use a ATX to dell adapter harness.

Cheers,

Hi all, thanks for the tips - yeah I'm defo not plugging ATX into it, and bit worried previous owner might've done that as was sold "untested". However looking at the Service Manual looks like the high voltages (+/-12V) are mapped to GND so might've just tripped the PSU? Anyway, I'm halfway trough mapping my own ATX adapter so we'll see....

I think I might've found something useful, Google for DOS tools to access PCI registers which are where the 430TX Cache Control registers are, showed me this VOGONs thread: TweakPCI - A DOS utility to view/modify PCI configuration registers

I'll be checking this out next to see if I can use it to examine and tinker with the Cache Control registers - well if I get the board runining that is...

maybe helpful info about FX chipset L2 cache CC register https://github.com/raszpl/430FXL2Cache. I just noticed I forgot to paste pci_write_dev, updating now

rasz_pl wrote on 2023-02-08, 13:22:

maybe helpful info about FX chipset L2 cache CC register https://github.com/raszpl/430FXL2Cache. I just noticed I forgot to paste pci_write_dev, updating now

That's very interesting thanks, seems like the 430FX has the same CC register. I really enjoy dissassembling old x86 ROMs and BIOS, I did a lot of dissassembly of the Zenith MFM-150 monitor/debug/test ROM code, which was fun. I've manged to figure out enough Ghidra to be dangerous 😀

I *think* using the TweakPCI tool, I might be able to disable L2 cache by running:

1tweakpci 7100 8086 b52 6=00

But will not know until (or if) I get my old motherboard running....

Oooh, looking at your post, I wonder if I also should set the SCFMI bit to '1' after disabling, hmmm?

afaik no need unless you are enabling cache and need to reset if first, 00 should suffice

rasz_pl wrote on 2023-02-08, 13:59:

afaik no need unless you are enabling cache and need to reset if first, 00 should suffice

So I did get my Optiplex GN+ Pentium MMX 166MHz board up and running, hurrah! As suspected the BIOS gives no L2 cache control so I eagerly tried my TweakPCI solutions and... nope, well it reported changing the Cache and then promptly hung the machine. I also tried setting Secondary Cache Force Miss or Invalidate (SCFMI) to 1 to try invalidating the cache first - also hung the machine. And disabling First Level Cache Enable (FLCE), also hang. I finally tried putting the Secondary Cache Size (SCS) to "00" in Autoexec.bat to see if doing it earlier in DOS's run stopped it crashing, nope, still hang. So maybe this is something that needs to be set by the BIOS during POST before RAM is active?

A little odd that setting Secondary Cache Force Miss or Invalidate (SCFMI) to '1' crashed it as the 430TX MTXC datasheet says that:

Software can flush the cache (cause all modified lines to be written back to DRAM) by setting SCFMI to a 1 with the L2 enabled (non-zero SCS, FLCE=1), and reading all L2 cache tag address locations. See FLCE bit description for FLCE/SCFMI interaction.

But maybe I need to do the tag reading before DOS trys to take back control? I know nothing of how cache works, so would need to LVL-UP to write something like "reading all L2 cache tag address locations"...

Interested if anyone has any thoughts on this.

TX L2 is writeback so you definitely need to force flush it before disabling. Flushing L1 is easy (wbinvd), L2 requires flat addressing or linearly mapped ram? Maybe just reading first 640KB of ram in 16bit mode would suffice as long as in real real mode, so no emm386 and probably no xmm loaded.

rasz_pl wrote on 2023-02-14, 16:24:

TX L2 is writeback so you definitely need to force flush it before disabling. Flushing L1 is easy (wbinvd), L2 requires flat addressing or linearly mapped ram? Maybe just reading first 640KB of ram in 16bit mode would suffice as long as in real real mode, so on emm386 and probably no xmm loaded.

Thanks, this is very helpful. Time to start skilling up on cache and see if I can write a little tool to disable the cache... Be a fun C/ASM project...