VOGONS


First post, by ryanfox81

User metadata
Rank Newbie
Rank
Newbie

Is there any way to use an 8bit 1MB 30 PIN SIMM module on the ISA BUS of an XT machine without any onboard DRAM?

or something along the lines of this instead?

https://github.com/homebrew8088/8088-PC-Compa … hQEx7mQMreFHl08

Just curious 😀

Reply 1 of 10, by rasz_pl

User metadata
Rank l33t
Rank
l33t

yes, but with additional dram controller. Why bother when 4Mbit SRAM chips are $4, thats why those cards exist https://www.lo-tech.co.uk/wiki/Lo-tech_1MB_RAM_Board much easier to design and build

Open Source AT&T Globalyst/NCR/FIC 486-GAC-2 proprietary Cache Module reproduction

Reply 2 of 10, by Anonymous Coward

User metadata
Rank l33t
Rank
l33t

It doesn't take SIMMs, but the original AST RAMPAGE can supposedly be configured to run on systems with 0kb onboard.
I tested this on my Juko NEST board that allows all onboard RAM to be disabled, but I couldn't get it going.

"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium

Reply 3 of 10, by Jo22

User metadata
Rank l33t++
Rank
l33t++

The original purpose of that feature was a different one, though.
If I understand correctly, these EMS boards supported back-filling in order to enhance memory management capabilities of an XT (or AT resp.).
See, the main flaw of a primitive 8086/8088 CPU is the lack of an MMU, a memory managment unit.
By replacing dumb motherboard memory by memory located on the intelligent EMS board (EEMS/LIM4),
programs like DESQView can swap in/out large amounts of memory, which is ideal for multi-tasking large DOS programs.
In essence, the EMS board takes the role of a memory controller or MMU.

Edit: I was just thinking out loud, no offense. Those Bocca RAM boards had SIMM slots, I remember.
No idea though, if they can work in 8-Bit slots, as well.

"Time, it seems, doesn't flow. For some it's fast, for some it's slow.
In what to one race is no time at all, another race can rise and fall..." - The Minstrel

//My video channel//

Reply 4 of 10, by Anonymous Coward

User metadata
Rank l33t
Rank
l33t

Most LIM4 and EEMS boards only allow you to backfill down to 256kb. The purpose of my experiment was to see if the entire 640kb could be backfilled. Perhaps with the right card/motherboard combo it might work?
I think I also tested this with an Orchid RAMQuest 8/16. That's a SIMM based card that takes up to 32MB. Í'm pretty sure this card sets the starting address via software, not using jumpers. I think I booted it up with 640K on the motherboard, ran the software utility to set the starting address to 0KB, disabled motherboard onboard memory and all I got was a black screen. This was over 10 years ago. I don't remember the specifics.

BTW, if the BocaRAM AT/Plus is the SIMM based card you're thinking of, then no, they don't work in 8-bit slots. I have two of these, and I couldn't make it work. There's nothing in the manual to indicate it should either.

"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium

Reply 5 of 10, by mkarcher

User metadata
Rank l33t
Rank
l33t
Anonymous Coward wrote on 2023-05-10, 02:29:

Most LIM4 and EEMS boards only allow you to backfill down to 256kb. The purpose of my experiment was to see if the entire 640kb could be backfilled. Perhaps with the right card/motherboard combo it might work?

You need to make sure that the motherboard doesn't drive the data bus when accessing the first 64k/256k of memory. If it does not have RAM data buffer chips, just not installing mainboard RAM chips is enough to keep the bus free. If it does have buffer chips, you need to find out how to disable them (jumpers?) or in case of socketed dedicated buffer chips just for memory pull them. Having an ISA card respond to memory starting at 0 is straighforward.

You might want to check into the 1M Lo-Tech SRAM card - possibly that one can provide memory in the first 64K.

Reply 6 of 10, by maxtherabbit

User metadata
Rank l33t
Rank
l33t
mkarcher wrote on 2023-05-10, 05:52:
Anonymous Coward wrote on 2023-05-10, 02:29:

Most LIM4 and EEMS boards only allow you to backfill down to 256kb. The purpose of my experiment was to see if the entire 640kb could be backfilled. Perhaps with the right card/motherboard combo it might work?

You need to make sure that the motherboard doesn't drive the data bus when accessing the first 64k/256k of memory. If it does not have RAM data buffer chips, just not installing mainboard RAM chips is enough to keep the bus free. If it does have buffer chips, you need to find out how to disable them (jumpers?) or in case of socketed dedicated buffer chips just for memory pull them. Having an ISA card respond to memory starting at 0 is straighforward.

You might want to check into the 1M Lo-Tech SRAM card - possibly that one can provide memory in the first 64K.

This presumes the onboard memory, buffered or no, is directly connected to the bus without any steering logic

Reply 7 of 10, by mkarcher

User metadata
Rank l33t
Rank
l33t
maxtherabbit wrote on 2023-05-10, 14:01:
mkarcher wrote on 2023-05-10, 05:52:

If it does not have RAM data buffer chips, just not installing mainboard RAM chips is enough to keep the bus free. If it does have buffer chips, you need to find out how to disable them (jumpers?) or in case of socketed dedicated buffer chips just for memory pull them.

This presumes the onboard memory, buffered or no, is directly connected to the bus without any steering logic

If I understand you correctly, the logic you call "steering logic" is what I meant when i wrote "data buffers". I'm thinking of something like a 74LS245 between the memory data pins and the system bus. If a 74LS245 drives the system bus during memory read from the first 64K, it will disturb an ISA card trying to serve a read from that address, whether memory is installed on the board or not.

If there is no steering logic / data buffers, there is no issue.

Reply 8 of 10, by maxtherabbit

User metadata
Rank l33t
Rank
l33t

I wasn't referring to bus transceivers. More like gating the memory read/write strobes from ever going active on the ISA slots if the onboard memory is serving the access.

Reply 9 of 10, by mkarcher

User metadata
Rank l33t
Rank
l33t
maxtherabbit wrote on 2023-05-10, 17:47:

I wasn't referring to bus transceivers. More like gating the memory read/write strobes from ever going active on the ISA slots if the onboard memory is serving the access.

OK, now I got what you meant. I will take a look into the 5150 64K mainboard schematics I have at hand shortly. I don't remember if there is steering for memory cycles, but IIRC there is steering for I/O cycles: On XT class machines, only I/O ports with A9 high (200-3FF) reach the ISA slots. Of course, the aliases 600-7FF, A00-BFF and so on work too, but the informal PC/XT platform definition also suggested that you don't decode the top 6 bits of I/O addresses. I/O ports 100-1FF only got available on the AT (and IBM immediately used 1F0-1F7 for the AT hard drive controller).

Reply 10 of 10, by mkarcher

User metadata
Rank l33t
Rank
l33t
maxtherabbit wrote on 2023-05-10, 17:47:

I wasn't referring to bus transceivers. More like gating the memory read/write strobes from ever going active on the ISA slots if the onboard memory is serving the access.

So, I got around to check the IBM schematics. Contrary to my previous post, there is no I/O steering. All I/O and memory read and writes reach the ISA bus. But most of the on-board components (ROMs, DMAC, PIT, PIC, keyboard interface) are located on the X-Bus which is connected to the ISA bus using a 74LS245 transceiver (U13). This transceiver is enabled on every bus cycle. The "direction" signal of this transceiver is "from X-bus to ISA bus" for memory reads from F000-FFFF and for I/O reads from 000..1FF (and all aliases). This occupies the ISA bus for the F segment and the low half of the PC I/O space.

The RAM is also connected using a transceiver from the memory data bus to the ISA bus (U12). This transceiver is enabled for access to the first 64K of address space, and transfers towards the ISA bus for all memory reads.

So for the original 5150 mainboard, you can not provide readable resources on the first 64K memory, the last 64K memory and I/O addresses with A9 clear, because that will fight transceivers on the mainboard. I suspect the 64K-256K 5150 board and the 5160 board to contain similar logic, but decoding the low 256K instead of the low 64K for onboard RAM.