Does anyone know what the tag ram socket on the P55T2P4 rev 3.10 motherboard is for? On the earlier rev boards I understand that you need to add an extra tag chip to have enough tag ram to cache the full 512M of ram (along with a coast module). However on rev 3.10, it doesn't make sense to me. The rev 3.10 board has no separate COASt slot because it is already maxed out at the max of 512KB of cache, and it would seem to have enough onboard tag to cache the full 512MB of supported ram.
My system has 96MB of RAM and with or without a tag chip installed, everything seems to behave the same in the 512MB position. If the board can cache 512M with the hardware onboard, what's the point of the tag slot?
I haven't been able to see any difference between having the jumper in the 64MB or the 512MB either (though the board won't post with a tag chip and the jumper in the 64MB position). Is there some kind of benchmark or test that would the performance of the cached vs uncached memory? cachechk seems to only go up to 64MB, so that's not much help.
You do need the 2nd TAG chip in order to enable the full 512MB cacheable area. It´s not about TAG size here but about expanding the TAG I/O bus from 8 to 11 bit.
You can check the difference with the tool "CTCM7".
If you run CTCM7 on your current configuration you will see that out of 96MB RAM only 64MB are cacheable. This means a performance loss if you run an OS that starts using RAM from the upper end like Win95 or 98.
If you are fine with just 64MB RAM you don´t need the second TAG chip. This is why ASUS and others left the 2nd TAG socket unpopulatated: They saved money and assumed many customer wouldn´t have more than 64MB RAM anyway and those who would could pay for the 2nd TAG chip themselves.
The effect also depends on what CPU you're running. If you have a K6-III(+) or K6-II+ installed that have built in 2nd Level Cache, the onboard Pipeline Burst cache becomes a 3rd level cache and you won't notice much difference in benchmarks. Those K6 models can cache up to 4GB RAM afaik.
Here are my results from CTCM without the tag chip, not sure what I'm supposed to be looking at 😕. It looks like ctcm is only looking at 64MB even though i have 96MB installed, just like cachechk.
Output of mem:
1Memory Type Total Used Free 2---------------- -------- -------- -------- 3Conventional 640K 94K 546K 4Upper 0K 0K 0K 5Reserved 384K 384K 0K 6Extended (XMS) 97,280K 68K 97,212K 7---------------- -------- -------- -------- 8Total memory 98,304K 546K 97,758K 9 10Total under 1 MB 640K 94K 546K 11 12Largest executable program size 546K (559,472 bytes) 13Largest free upper memory block 0K (0 bytes) 14MS-DOS is resident in the high memory area.
Results from ctcm. 512MB cache position, no extra tag ram chip:
1Uses Pentium Timer, Pentium clock : 233.9 MHz 2Pentiummsr=TRUE 3XMM-Version: 3.00 Internal Revision No. : 3.515 HMA available. 4available extended Memory : 65535 KBytes. 5Largest Block :65535 KBytes. 665535 KBytes requested . Handle = 54680 7from addr.: 00111000 8 9 10CTCM, translated by Thomas Pabst, copyright ct-Mag. V1.5b/t2 11Processor-Timing : Pentium 12Processor CPUID : Pentium/ Typ:00 Fam:05 Mod:04 Stp:03 13Clck : 233.9 MHz 14internal Bus : 32 Bit between CPU and primary Cache or Memory 15FPU : Pentium 16L1 Cache : 16 KByte,4-way associative 17L2 Cache : 512 KByte, direct mapped 18Write Strategy L1 : Write Back 19Write Strategy L2 : Write Back 20Dirty Tag L2 : ok 21 22 Through Put & Bus Performance: Main Memory from 00111000 23 24Best Time for 16K MOVSD (Cache /Page Hits) : 17 mcs - 958.4 MByte/s 25average t. for 16K MOVSD (Miss + Hit) : 222 mcs - 73.9 MByte/s 26average t. for 16K MOVSD (if clean) : 276 mcs - 59.3 MByte/s 27average t. for 16K MOVSD (if dirty) : 247 mcs - 66.3 MByte/s 28Main Memory 16K MOVSD (Cache misses) : 392 mcs - 41.8 MByte/s 29 30average with 512 KB L2-Cache /DOS (640K) : 202 mcs - 81.0 MByte/s 31average with 512 KB L2-Cache /WIN (4M ) : 252 mcs - 65.0 MByte/s 32
Results from ctcm. 512MB cache position, with extra tag ram chip:
1Uses Pentium Timer, Pentium clock : 233.9 MHz 2Pentiummsr=TRUE 3XMM-Version: 3.00 Internal Revision No. : 3.515 HMA available. 4available extended Memory : 65535 KBytes. 5Largest Block :65535 KBytes. 665535 KBytes requested . Handle = 54680 7from addr.: 00111000 8 9 10CTCM, translated by Thomas Pabst, copyright ct-Mag. V1.5b/t2 11Processor-Timing : Pentium 12Processor CPUID : Pentium/ Typ:00 Fam:05 Mod:04 Stp:03 13Clck : 233.9 MHz 14internal Bus : 32 Bit between CPU and primary Cache or Memory 15FPU : Pentium 16L1 Cache : 16 KByte,4-way associative 17L2 Cache : 512 KByte, direct mapped 18Write Strategy L1 : Write Back 19Write Strategy L2 : Write Back 20Dirty Tag L2 : ok 21 22 Through Put & Bus Performance: Main Memory from 00111000 23 24Best Time for 16K MOVSD (Cache /Page Hits) : 17 mcs - 958.2 MByte/s 25average t. for 16K MOVSD (Miss + Hit) : 222 mcs - 73.8 MByte/s 26average t. for 16K MOVSD (if clean) : 276 mcs - 59.3 MByte/s 27average t. for 16K MOVSD (if dirty) : 247 mcs - 66.3 MByte/s 28Main Memory 16K MOVSD (Cache misses) : 392 mcs - 41.8 MByte/s 29 30average with 512 KB L2-Cache /DOS (640K) : 202 mcs - 80.9 MByte/s 31average with 512 KB L2-Cache /WIN (4M ) : 252 mcs - 65.0 MByte/s
Yes as stated above that means only the first 64MB is properly L2 cached w/o the extra TAG. Can you post a picture of your cache module? It seems there was no variation in the /WIN 4M....
If cache module already has a TAG you cannot also insert a extra TAG chip... or maybe I am reading it all wrong...
Hate posting a reply and then have to edit it because it made no sense 😁 First computer was an IBM 3270 workstation with CGA monitor. Stuff: https://archive.org/details/@horun
The reason why I recommended you use CTCM"7" (seven!) is that it´s results are more straight forward. It explicitly tells you the cacheable areas of L1 and L2.
The reason why I recommended you use CTCM"7" (seven!) is that it´s results are more straight forward. It explicitly tells you the cacheable areas of L1 and L2.
Thanks for the copy of CTCM7. That was a really hard piece of software to find.
Just like you guys said, CTCM7 shows the expected results of caching 64MB+ with the tag installed and the jumper in the 512MB position. I appreciate you taking the time to clarify and explain what the jumper and the tag ram really do on this board. After this testing, it seems the jumper could have simply been left out and hard wired in the 512MB position, and then the presence of a tag ram (or not) would determine whether the ram above 64MB was cached or not.
Here's a picture of my tag ram, ISSI IS61C256AH-12N
Tag ram IC installed, 512MB jumper position
1Processor Timing : Pentium,Pentium-MMX 2Processor CPUID : GenuineIntel Typ=00 Fam=05 Mod=04 Rev=03 Feat=008001BF 3Processor Name : Pentium-MMX 4Actual clock rate : 233.841 MHz, according to Pentium Timer:233.871 MHz 5Primary Cache (L1) : 16 KByte,4way associative 6Secondary Cache (L2): 512 KByte,direct mapped 7Code Cache (L1) : 16 KByte,4way associative 8Main memory : 96 MByte, no Memory holes found 9Cacheable Area L1 : 96 MByte, no noncacheable Areas found 10Cacheable Area L2 : 96 MByte, no noncacheable Areas found 11Write Strategy L1 : Write Back, no Write Allocation, linear Fill,Pseudo-LRU 12Write Strategy L2 : Write Back, No Write Allocation, no L2 Flush (wbinvd) 13Dirty Tag L2 : ok
No Tag ram IC installed, 512MB jumper position.
Everything appears to work just fine without the tag ram, but ctcm7 does show that memory above 64MB isn't being cached.
1Processor Timing : Pentium,Pentium-MMX 2Processor CPUID : GenuineIntel Typ=00 Fam=05 Mod=04 Rev=03 Feat=008001BF 3Processor Name : Pentium-MMX 4Actual clock rate : 233.841 MHz, according to Pentium Timer:233.872 MHz 5Primary Cache (L1) : 16 KByte,4way associative 6Secondary Cache (L2): 512 KByte,direct mapped 7Code Cache (L1) : 16 KByte,4way associative 8Main memory : 96 MByte, no Memory holes found 9Cacheable Area L1 : 96 MByte, no noncacheable Areas found 10Cacheable Area L2 : 64 MByte, Cache Area < Main memory!! 11Write Strategy L1 : Write Back, no Write Allocation, linear Fill,Pseudo-LRU 12Write Strategy L2 : Write Back, No Write Allocation, no L2 Flush (wbinvd) 13Dirty Tag L2 : ok
And then just for completeness
No Tag ram IC installed, 64MB jumper position (same result)
1Processor Timing : Pentium,Pentium-MMX 2Processor CPUID : GenuineIntel Typ=00 Fam=05 Mod=04 Rev=03 Feat=008001BF 3Processor Name : Pentium-MMX 4Actual clock rate : 233.903 MHz, according to Pentium Timer:233.872 MHz 5Primary Cache (L1) : 16 KByte,4way associative 6Secondary Cache (L2): 512 KByte,direct mapped 7Code Cache (L1) : 16 KByte,4way associative 8Main memory : 96 MByte, no Memory holes found 9Cacheable Area L1 : 96 MByte, no noncacheable Areas found 10Cacheable Area L2 : 64 MByte, Cache Area < Main memory!! 11Write Strategy L1 : Write Back, no Write Allocation, linear Fill,Pseudo-LRU 12Write Strategy L2 : Write Back, No Write Allocation, no L2 Flush (wbinvd) 13Dirty Tag L2 : ok
