Order a second cpu and test your theory.
Or try memtest 86+

yeah ! Could be bad CPU but that is rare. Can you post a picture of the top and bottom of the CPU ? maybe a fake or one rev that has known issues...

Bad CPU is not the first thing I would think of, especially if it is in good physical condition and it works fine in WT mode.

L1 WB cache support on 486 motherboards is hit and miss (pun intended), so the first thing to know would be what board you are using, jumper settings, etc.

When it comes to L1 WB in particular, try turning off the "DRAM Write Burst" option in the BIOS if there's one. I noticed that one would always cause problems similar to the ones you describe.

The 2 motherboards I have tried it on are LS-486E Rev D and Dataexpert EXP4045.
In LS-486E it supports the supports that cpu directly at least based on manual and so far I have figured out that jumper at pins 6-7 of JP8 changes between WB and WT cache modes and jumper at pins 3-4 of JP6 control multiplier between 3x and 4x. The cpu cant be fake because as far as I know other cpus dont have the 4x multiplier and it shows 16kb internal cache in speedsys and cachechk.

Dataexpert EXP4045 does not have direct support for am5x86 and bios is from few months before release of the cpu. BIOS version 2.3 from July 1995 which is newer than the bios version on retroweb. I have tested that jumper JP32 closed changes to WB mode and when the jumper is open it changes to WT mode. Multiplier is controlled by JP16. When pins 7-8 are closed it is 4x and when jumper is removed it is 3x.

https://theretroweb.com/motherboard/manual/32985.pdf

Best option would probably try to find another similar cpu to test with if there are no bios options that can cause this kind of behaviour.

Baoran wrote on 2023-07-12, 08:49:

so far I have figured out that jumper at pins 6-7 of JP8 changes between WB and WT cache modes

It takes more than that to properly support WB on a 486 system, quite a few other signals must be connected as well - and perhaps aren't. Just telling the CPU to use WB instead of WT is not enough if the cache coherency protocol between CPU and chipset is not done right.

That floppy corruption issue you get is a very good way to tell WB is not working because the chipset is not pullig data from CPU internal L1 during DMA cycles to floppy drive. So you can use that as quick test if the mobo is set correctly for WB operation or not.

Deunan wrote on 2023-07-12, 10:08:

Baoran wrote on 2023-07-12, 08:49:

so far I have figured out that jumper at pins 6-7 of JP8 changes between WB and WT cache modes

It takes more than that to properly support WB on a 486 system, quite a few other signals must be connected as well - and perhaps aren't. Just telling the CPU to use WB instead of WT is not enough if the cache coherency protocol between CPU and chipset is not done right.

That floppy corruption issue you get is a very good way to tell WB is not working because the chipset is not pullig data from CPU internal L1 during DMA cycles to floppy drive. So you can use that as quick test if the mobo is set correctly for WB operation or not.

If all the other jumpers have been set correctly for AMD-X5-P75 like in the picture doesn't that mean that all the other signals for WB should be correct since CHKCPU shows it is in WB mode with those jumper settings? I mean all I know is that if I remove that one jumper from pins 6-7 of JP8 while all the other jumpers are the same everything works fine and CHKCPU program shows that it it has changed to WT mode. I can still run any program that is already on hard drive when it is in WB mode as long as I dont need anything from a floppy and it shows speed increase. Speedsys shows cpu score of 42 when in WT mode and 50 when in WB mode.

Baoran wrote on 2023-07-12, 10:42:

I mean all I know is that if I remove that one jumper from pins 6-7 of JP8 while all the other jumpers are the same everything works fine and CHKCPU program shows that it it has changed to WT mode.

WT is way easier to implement than WB. So simply moving that one jumper is "fixing" the problem, yes, but it's not the cause of it. And DOS doesn't use DMA for HDD access so everything will seem to work there even in WB mode.

WB will fail during DMA writes and (if this is a PCI system) when a card capable of bus-mastering is bypassing the CPU to access RAM (so, a DMA in essence but done more modern way). Shouldn't happen in DOS but might in Windows (if the card supports any 2D acceleration) or perhaps some games if it's a 3D card of some sort. Or it's if it a SCSI HDD controller for example. DMA is used for floppy, and you only care about writes, any reads from floppies will work as long as you don't try to change the data on it. SoundBlaster type cards also use DMA and might output wrong sounds.

Point here is, the WB mode is not working correctly. Perhaps the mobo doesn't really support it, the manual might be for a different PCB revision or was written without testing the CPU with the assumption it would work just like Intel - and AFAIR there are some differences (there sure are for Cyrix CPUs). It's not impossible but very unlikely that the L1 cache on the CPU works properly but only in WT mode.

As it was already suggested there might also be some BIOS settings that need to be configured in a certain way in addition to all the jumpers. This too might be CPU-brand specific.

Deunan wrote on 2023-07-12, 11:42:

WT is way easier to implement than WB. So simply moving that one jumper is "fixing" the problem, yes, but it's not the cause of […]
Show full quote

Baoran wrote on 2023-07-12, 10:42:

I mean all I know is that if I remove that one jumper from pins 6-7 of JP8 while all the other jumpers are the same everything works fine and CHKCPU program shows that it it has changed to WT mode.

WT is way easier to implement than WB. So simply moving that one jumper is "fixing" the problem, yes, but it's not the cause of it. And DOS doesn't use DMA for HDD access so everything will seem to work there even in WB mode.

WB will fail during DMA writes and (if this is a PCI system) when a card capable of bus-mastering is bypassing the CPU to access RAM (so, a DMA in essence but done more modern way). Shouldn't happen in DOS but might in Windows (if the card supports any 2D acceleration) or perhaps some games if it's a 3D card of some sort. Or it's if it a SCSI HDD controller for example. DMA is used for floppy, and you only care about writes, any reads from floppies will work as long as you don't try to change the data on it. SoundBlaster type cards also use DMA and might output wrong sounds.

Point here is, the WB mode is not working correctly. Perhaps the mobo doesn't really support it, the manual might be for a different PCB revision or was written without testing the CPU with the assumption it would work just like Intel - and AFAIR there are some differences (there sure are for Cyrix CPUs). It's not impossible but very unlikely that the L1 cache on the CPU works properly but only in WT mode.

As it was already suggested there might also be some BIOS settings that need to be configured in a certain way in addition to all the jumpers. This too might be CPU-brand specific.

How does this apply with 2 motherboards having exactly same symptoms including system freezing when trying to slow down the system using turbo button when in WB more? Especially when one of them is PCI motherboard and the other one is VLB motherboard? The LS-486E PCI motherboard was made in 1996 which is way after that cpu was released. I could understand this if the problem was only with the vlb board that has made before the cpu was released.

Baoran wrote on 2023-07-12, 12:59:

How does this apply with 2 motherboards having exactly same symptoms including system freezing when trying to slow down the system using turbo button when in WB more? Especially when one of them is PCI motherboard and the other one is VLB motherboard? The LS-486E PCI motherboard was made in 1996 which is way after that cpu was released. I could understand this if the problem was only with the vlb board that has made before the cpu was released.

Hi Baoran,

I don’t have a ready explanation about the LS-486E Rev D board, the Am5x86 in L1 cache Write-Back mode should just work.
But the problem with the DataExpert EXP4045 is most probably a BIOS issue! What does the BIOS display as CPU type when you run the Am5x86 in x4 multiplier mode?

In addition to the excellent replies from @Deunan, explaining the need of connecting 2 or 3 extra signal lines between the CPU and chipset to get L1 WB working, the BIOS plays a role here too. The BIOS, when detecting a WB capable CPU and this CPU is jumpered for WB mode, must program the chipset registers for the L1 cache WB protocol and enable the extra signal lines.
Failing to do so will result in the WB problems you described.

On the EXP4045 board, you can test the correct functioning of this L1 WB CPU/chipset/BIOS dance by setting the Am5x86 in x3 multiplier mode. In this mode, the Am5x86 will behave exactly like an Enhanced Am486DX4 CPU including its CPUID and L1 WB mode support.
Because your July 1995 BIOS supports this Enhanced Am486DX4 CPU, it should report this CPU on the boot screens and let the Am5x86 work correctly in x3 multiplier and L1 WB mode.

If this works fine now (try booting from a bootable floppy as ultimate test) you know the jumpers are set correctly and the Am5x86 is good. But you need a BIOS update. 😉

Can you post a dump of the EXP4045 v2.3 BIOS here so I can help you with an update?

Greetings, Jan

Edit: Did you see my old Am5x86 article about getting this CPU running on most socket 3 boards? It is still available on my website:
http://www.steunebrink.info/amd5x86.htm

Chkcpu wrote on 2023-07-12, 14:18:

Hi Baoran, […]
Show full quote

Baoran wrote on 2023-07-12, 12:59:

How does this apply with 2 motherboards having exactly same symptoms including system freezing when trying to slow down the system using turbo button when in WB more? Especially when one of them is PCI motherboard and the other one is VLB motherboard? The LS-486E PCI motherboard was made in 1996 which is way after that cpu was released. I could understand this if the problem was only with the vlb board that has made before the cpu was released.

Hi Baoran,

I don’t have a ready explanation about the LS-486E Rev D board, the Am5x86 in L1 cache Write-Back mode should just work.
But the problem with the DataExpert EXP4045 is most probably a BIOS issue! What does the BIOS display as CPU type when you run the Am5x86 in x4 multiplier mode?

In addition to the excellent replies from @Deunan, explaining the need of connecting 2 or 3 extra signal lines between the CPU and chipset to get L1 WB working, the BIOS plays a role here too. The BIOS, when detecting a WB capable CPU and this CPU is jumpered for WB mode, must program the chipset registers for the L1 cache WB protocol and enable the extra signal lines.
Failing to do so will result in the WB problems you described.

On the EXP4045 board, you can test the correct functioning of this L1 WB CPU/chipset/BIOS dance by setting the Am5x86 in x3 multiplier mode. In this mode, the Am5x86 will behave exactly like an Enhanced Am486DX4 CPU including its CPUID and L1 WB mode support.
Because your July 1995 BIOS supports this Enhanced Am486DX4 CPU, it should report this CPU on the boot screens and let the Am5x86 work correctly in x3 multiplier and L1 WB mode.

If this works fine now (try booting from a bootable floppy as ultimate test) you know the jumpers are set correctly and the Am5x86 is good. But you need a BIOS update. 😉

Can you post a dump of the EXP4045 v2.3 BIOS here so I can help you with an update?

Greetings, Jan

Edit: Did you see my old Am5x86 article about getting this CPU running on most socket 3 boards? It is still available on my website:
http://www.steunebrink.info/amd5x86.htm

Exp4045 motherboard thinks it is a 120Mhz am486dx4-S during post when in 4x mode and 100Mhz am486dx-s when it is in 3x mode. Changing multiplier does not make any difference when it comes to problems. Only thing that makes floppy and turbo button work normally is removing JP16 that changes what CHKCPU reports from Write back to Write through and makes the system slower too showing in speedsys score that I mentioned earlier.

Only reason I managed to make things work properly on the LS-486E motherboard at all was because the symptoms were the same exactly the same as on EXP4045 motherboard and that made me start searching for a jumper that would change it from WB to WT mode and I removed jumpers one at the time until removing jumper from pins 6-7 of JP8 made it change to WT and that also fixed the turbo button and floppy drive issues the same way as that removing jumper JP32 on EXP4045 fixed them. I probably would not have thought it strange WB not working on EXP4045 if the symptoms would not have been exactly the same on a motherboard that is suppose to support the cpu and WB on it normally. It also means I get performance improvement on EXP4045 motherboard too and I can run software normally on hard drive as long as I dont need to use floppy drive or touch the turbo button.

I'm going to have to see if I can get the bios dumped. I have only used the flash programmer few times before in the past.
I am still suspicious of the cpu being faulty though as long as it doesn't work on the LS-486E motherboard either and symptoms are identical. I would be happy if I would get it to work on either of the motherboards since they are the only ones I have with support for low voltage 486 cpus.

Chkcpu wrote on 2023-07-12, 14:18:

Hi Baoran, […]
Show full quote

Baoran wrote on 2023-07-12, 12:59:

How does this apply with 2 motherboards having exactly same symptoms including system freezing when trying to slow down the system using turbo button when in WB more? Especially when one of them is PCI motherboard and the other one is VLB motherboard? The LS-486E PCI motherboard was made in 1996 which is way after that cpu was released. I could understand this if the problem was only with the vlb board that has made before the cpu was released.

Hi Baoran,

I don’t have a ready explanation about the LS-486E Rev D board, the Am5x86 in L1 cache Write-Back mode should just work.
But the problem with the DataExpert EXP4045 is most probably a BIOS issue! What does the BIOS display as CPU type when you run the Am5x86 in x4 multiplier mode?

In addition to the excellent replies from @Deunan, explaining the need of connecting 2 or 3 extra signal lines between the CPU and chipset to get L1 WB working, the BIOS plays a role here too. The BIOS, when detecting a WB capable CPU and this CPU is jumpered for WB mode, must program the chipset registers for the L1 cache WB protocol and enable the extra signal lines.
Failing to do so will result in the WB problems you described.

On the EXP4045 board, you can test the correct functioning of this L1 WB CPU/chipset/BIOS dance by setting the Am5x86 in x3 multiplier mode. In this mode, the Am5x86 will behave exactly like an Enhanced Am486DX4 CPU including its CPUID and L1 WB mode support.
Because your July 1995 BIOS supports this Enhanced Am486DX4 CPU, it should report this CPU on the boot screens and let the Am5x86 work correctly in x3 multiplier and L1 WB mode.

If this works fine now (try booting from a bootable floppy as ultimate test) you know the jumpers are set correctly and the Am5x86 is good. But you need a BIOS update. 😉

Can you post a dump of the EXP4045 v2.3 BIOS here so I can help you with an update?

Greetings, Jan

Edit: Did you see my old Am5x86 article about getting this CPU running on most socket 3 boards? It is still available on my website:
http://www.steunebrink.info/amd5x86.htm

Here is the bios dump from the EXP4045 motherboard. I dont have UV light to erase the bios chip right now though.

Thanks for the v2.3 BIOS dump.
A first look to the CPUID tables with a hexeditor shows the expected Enhanced Am486DX2/4 support, but no Am5x86 support.

But when checking this BIOS with Award’s Modbin tool, I found a hidden “Internal Cache WB/WT” option that was fixed at “Write Thru”. So unless this BIOS is able to unhide this option for specific CPUs, or has automatic WB/WT logic for WB capable CPUs, it is unable to set the L1 WB protocol in the chipset!
I already started to disassemble the BIOS to find out what is going on here. However, the analysis will take a while. 😉

Another curious find is an “Internal Cache WB Burst” option. A Write-Back of L1 cache data to the L2 cache or main memory is per definition a burst write. But this option allows to disable this. Strange, never seen that before on other 486 chipsets.
Also strange that this option is available while the L1 cache can’t be switched to WB in the first place…

Unfortunately I don’t have the datasheet of this rare Symphony SL82C491 chipset, but I hope to find out how the L1 WB enable function works by comparing the BIOS logic with that from other L1 WB capable 486 chipsets.
I will report back when I have more.

Jan

Chkcpu wrote on 2023-07-13, 11:31:

Thanks for the v2.3 BIOS dump. A first look to the CPUID tables with a hexeditor shows the expected Enhanced Am486DX2/4 support, […]
Show full quote

Thanks for the v2.3 BIOS dump.
A first look to the CPUID tables with a hexeditor shows the expected Enhanced Am486DX2/4 support, but no Am5x86 support.

But when checking this BIOS with Award’s Modbin tool, I found a hidden “Internal Cache WB/WT” option that was fixed at “Write Thru”. So unless this BIOS is able to unhide this option for specific CPUs, or has automatic WB/WT logic for WB capable CPUs, it is unable to set the L1 WB protocol in the chipset!
I already started to disassemble the BIOS to find out what is going on here. However, the analysis will take a while. 😉

Another curious find is an “Internal Cache WB Burst” option. A Write-Back of L1 cache data to the L2 cache or main memory is per definition a burst write. But this option allows to disable this. Strange, never seen that before on other 486 chipsets.
Also strange that this option is available while the L1 cache can’t be switched to WB in the first place…

Unfortunately I don’t have the datasheet of this rare Symphony SL82C491 chipset, but I hope to find out how the L1 WB enable function works by comparing the BIOS logic with that from other L1 WB capable 486 chipsets.
I will report back when I have more.

Jan

Thanks.
Yeah. The chipset seems to have many names. Seen it being called expertchip, winbond or that symphony wagner.
Do you happen to know if there would be a compatible EEPROM chip that I could use instead of the original EPROM for bios on that motherboard? The original EPROM seems to be TMS 27c512-12.

Baoran wrote on 2023-07-13, 16:28:

Thanks.
Yeah. The chipset seems to have many names. Seen it being called expertchip, winbond or that symphony wagner.
Do you happen to know if there would be a compatible EEPROM chip that I could use instead of the original EPROM for bios on that motherboard? The original EPROM seems to be TMS 27c512-12.

Yes, it is a good idea to buy a new (E)EPROM to program the updated BIOS and keep the original EPROM as backup. For these BIOS experiments I advice to use a Winbond W27C512 EEPROM. These are compatible with 27C512 UV-EPROMs but can be electrically ereased for re-programming. No hassle with UV-light anymore.
But you still need an external programmer to program the BIOS in the (E)EPROM chip. 😉

Jan

Chkcpu wrote on 2023-07-13, 17:16:

Yes, it is a good idea to buy a new (E)EPROM to program the updated BIOS and keep the original EPROM as backup. For these BIOS e […]
Show full quote

Baoran wrote on 2023-07-13, 16:28:

Thanks.
Yeah. The chipset seems to have many names. Seen it being called expertchip, winbond or that symphony wagner.
Do you happen to know if there would be a compatible EEPROM chip that I could use instead of the original EPROM for bios on that motherboard? The original EPROM seems to be TMS 27c512-12.

Yes, it is a good idea to buy a new (E)EPROM to program the updated BIOS and keep the original EPROM as backup. For these BIOS experiments I advice to use a Winbond W27C512 EEPROM. These are compatible with 27C512 UV-EPROMs but can be electrically ereased for re-programming. No hassle with UV-light anymore.
But you still need an external programmer to program the BIOS in the (E)EPROM chip. 😉

W27C512.pdf

Jan

Thanks. That is not a problem because I used such programmer to dump the bios in the first place.

Chkcpu wrote on 2023-07-13, 11:31:

Another curious find is an “Internal Cache WB Burst” option. A Write-Back of L1 cache data to the L2 cache or main memory is per definition a burst write. But this option allows to disable this.

IIRC the Cyrix CPUs had, at first, their own WB protocol that was not compatible with Intel. I vaguely recall something about that burst write but I can't remember any details.

Chkcpu wrote on 2023-07-13, 11:31:

But when checking this BIOS with Award’s Modbin tool, I found a hidden “Internal Cache WB/WT” option that was fixed at “Write Thru”. So unless this BIOS is able to unhide this option for specific CPUs, or has automatic WB/WT logic for WB capable CPUs, it is unable to set the L1 WB protocol in the chipset!
I already started to disassemble the BIOS to find out what is going on here. However, the analysis will take a while. 😉

The usual behaviour on 486 BIOSes is that the L1 WB/WT option only affects Cyrix CPUs that use CR0 to configure WB/WT (and some control bit in a Cyrix proprietary register to lock a bit in CR0 to prevent Intel software from disabling WB). The configuration of the chipset is supposed to depend on the CPUID from the table you already looked at. If that table indicates a CPU that uses the Intel WB protocol (i.e. Pentium Overdrive, Intel 486 &EW, AMD Enhanced DX2/DX4/5x86), the chipset is set up correctly for WB operation, no matter how this hidden option is configured.

mkarcher wrote on 2023-07-13, 18:26:

The usual behaviour on 486 BIOSes is that the L1 WB/WT option only affects Cyrix CPUs that use CR0 to configure WB/WT (and some control bit in a Cyrix proprietary register to lock a bit in CR0 to prevent Intel software from disabling WB). The configuration of the chipset is supposed to depend on the CPUID from the table you already looked at. If that table indicates a CPU that uses the Intel WB protocol (i.e. Pentium Overdrive, Intel 486 &EW, AMD Enhanced DX2/DX4/5x86), the chipset is set up correctly for WB operation, no matter how this hidden option is configured.

Hi mkarcher,

Thanks for sharing your thoughts on this L1 cache WB issue.
I fully agree that on 486 BIOSes the BIOS is supposed to setup the chipset registers for L1 WB operation automatically, depending on the data it got from Intel/AMD CPUs when using the CPUID instruction during CPU detection. But I’ve seen enough deviations, especially in 1994 and early 1995 BIOSes, to make me skeptical about the correct implementation of this logic.

From March 1995 onwards, Award started to use CPUID tables in its BIOS and implemented a previously reserved CMOS register bit (Register 3Fh bit 3) to hold a “CPU in L1 WB mode” flag to serve the logic you described. I found that by August 1995 this automatic L1 WB logic was present in every Award 486 BIOS I looked at. So it is likely that I find it in the July 1995 BIOS from the OP as well and that this hidden L1 cache WB/WT BIOS option only hampers WB selection on Cyrix CPUs.

Before March 1995, Award primarily used the Reset_ID from the DX register for CPU detection, including the P24D when used in WT mode (therefore it is shown as a regular 486DX2). But there are 2 exceptions:
1. In the 1994 BIOS a hardcoded GenuineIntel CPUID Signature 047xh check is made to detect the P24D in WB mode.
2. In BIOSes from December 1994 up to February 1995, an additional hardcoded check on AuthenticAMD CPUID Signatures 047xh and 049xh is made to detect the Enhanced Am486DX2/4.
Although the BIOS could have used this early hardcoded CPUID detection for automatic L1 WB chipset programing, I never found one that did.
So in these 1994 and early 1995 Award BIOSes you still had to set the L1 Cache WB/WT option to match the setting of the WB/WT jumper when running a WB capable AMD/Intel CPU.

The above all concerns the Award BIOS and its possible that the AMI BIOS performed better in this respect. Unfortunately my knowledge about the AMI BIOS inner workings is lacking, so I wouldn’t know. 😉

Regards, Jan

Chkcpu wrote on 2023-07-17, 19:25:

From March 1995 onwards, Award started to use CPUID tables in its BIOS and implemented a previously reserved CMOS register bit (Register 3Fh bit 3) to hold a “CPU in L1 WB mode” flag to serve the logic you described.

So it seems I never looked at earlier BIOSes for WB capable chipsets. Although I think I've seen BIOSes use the CPU type code in CMOS 3B, bits 1-6 to select the chipset WB/WT mode. This bit field is also derived from Reset_DX (and overwritten on Cyrix CPUs). If a Pentium Overdrive was dected using Reset_DX, the chipset got programmed into WB mode.

That was a Saturn II board - and I never got it working with L1WB. All invalidate cycles (INVD, WBINVD) sent the north bridge / system controller into an endless loop. The BIOS reconfigured the chipset into WT mode before invalidation, so it is likely a known chipset bug.

Chkcpu wrote on 2023-07-17, 19:25:

Before March 1995, Award primarily used the Reset_ID from the DX register for CPU detection, including the P24D when used in WT mode (therefore it is shown as a regular 486DX2). But there are 2 exceptions:
1. In the 1994 BIOS a hardcoded GenuineIntel CPUID Signature 047xh check is made to detect the P24D in WB mode.
2. In BIOSes from December 1994 up to February 1995, an additional hardcoded check on AuthenticAMD CPUID Signatures 047xh and 049xh is made to detect the Enhanced Am486DX2/4.

I don't see the point in using CPUID here, except for a nice user display. The CPUID signature is identical to Reset_DX, and 047x is the Intel &EW protocol, whether the CPU is Intel or AMD.

Award also derives the clock multiplier from Reset_DX. It later measures the processor performance to geht the CPU clock and then derives the bus clock for autoconfig by dividing by the clock multiplier. Do you know how Awaerd dealt with the AMD DX4 NV8T (no CPUID support, and the same Reset_DX 42x in both x2 and x3 mode)? If you detect a no-CPUID DX2-type CPU at 100MHz, it can be an NV8T at either 3x33 or at 2x50.

Chkcpu wrote on 2023-07-17, 19:25:

Regards, Jan

Thanks for your elaborate reply!