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Cpu write back cache causing issues.

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Reply 40 of 60, by Baoran

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Chkcpu wrote on 2023-07-23, 16:10:
Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode! The iDX4 is basical […]
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Baoran wrote on 2023-07-23, 13:48:

Jumpers are set exactly like for 80486dx4 based on https://theretroweb.com/motherboard/manual/32985.pdf jumper manual except JP16 that controls the multiplier needs to be set to similar to 2x in the table in that pdf to get 4x multiplier.

Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode!
The iDX4 is basically a L1 Cache WT only CPU. Okay, Intel later made a WB Enhanced DX4 version, but the jumpers for that model are not in this manual.

A way out of this jumper hell is this nice resource:
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm
In the table below the socket diagram, you can see that (except for the P24T) all WB capable 486 CPUs from Intel and AMD use the same pins for the essential L1 WB signals INV (A10), HITM (A12), CACHE (B12), and WB/WT (B13).

The jumper settings for iDX4-WB, Am486DX2-WB, Am486DX4-WB, and Am5x86 are not in the manual. But luckily the settings for the P24D (i486DX2-WB) are, so you can use those for the Am5x86!

The only deviation of course is to keep the CPU Voltage selection on 3.3V!! 😉

Without the JP16 7-8 jumper, the Am5x86 should now run correctly in x3 multiplier and L1 cache WB mode with the v2.3 BIOS. I really hope this works!

Jan

Why JP32 closed turns on WB cache and it is aldo closed in dx4 settings then?

Reply 41 of 60, by Chkcpu

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Baoran wrote on 2023-07-23, 18:21:
Chkcpu wrote on 2023-07-23, 16:10:
Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode! The iDX4 is basical […]
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Baoran wrote on 2023-07-23, 13:48:

Jumpers are set exactly like for 80486dx4 based on https://theretroweb.com/motherboard/manual/32985.pdf jumper manual except JP16 that controls the multiplier needs to be set to similar to 2x in the table in that pdf to get 4x multiplier.

Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode!
The iDX4 is basically a L1 Cache WT only CPU. Okay, Intel later made a WB Enhanced DX4 version, but the jumpers for that model are not in this manual.

A way out of this jumper hell is this nice resource:
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm
In the table below the socket diagram, you can see that (except for the P24T) all WB capable 486 CPUs from Intel and AMD use the same pins for the essential L1 WB signals INV (A10), HITM (A12), CACHE (B12), and WB/WT (B13).

The jumper settings for iDX4-WB, Am486DX2-WB, Am486DX4-WB, and Am5x86 are not in the manual. But luckily the settings for the P24D (i486DX2-WB) are, so you can use those for the Am5x86!

The only deviation of course is to keep the CPU Voltage selection on 3.3V!! 😉

Without the JP16 7-8 jumper, the Am5x86 should now run correctly in x3 multiplier and L1 cache WB mode with the v2.3 BIOS. I really hope this works!

Jan

Why JP32 closed turns on WB cache and it is aldo closed in dx4 settings then?

Yes, this is confusing.
A possible explanation is that the 80486DX4 jumper settings are for both the regular Intel DX4 as well as the AMD 486DX4 NV8T. These are both L1 cache WT-only CPUs.

The Am486DX4 NV8T uses pin B13 as CLKMUL, the same pin that the iDX4-WB uses for WB/WT. So JP32 must be closed to get an Am486DX4 NV8T in x3 multiplier mode. This 80486DX4 jumper setting works for the Am486DX4 NV8T and the regular iDX4 because B13 is an INC pin (Internally Not Connected) on the regular iDX4.

The JP16 7-8 jumper setting also works for both DX4 models because it controls pin R17 that is CLKMUL on the iDX4 and INC on the Am486DX4 NV8T.

But the 80486DX4 jumper setting are still missing the required HITM and CACHE signal connections that the P24D settings have. So just try the P24D settings and see where it gets you. 😉

Jan

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Reply 42 of 60, by Deunan

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Chkcpu wrote on 2023-07-21, 17:49:

The most noticeable function change is about the "CACHE" and "PCD" signals on chipset pin 118.

It seems I may have found an issue with my mobo, which would also explain why some sources claim that SiS 471 can only do WB on PODP chips but not 486WB. It looks like G1 (on PODP outline) can be jumpered to PCD pin, but B12 is completly unconnected on this mobo. Well, a simple wire can fix that but I didn't notice it earlier due to some typing mistakes in my original investigation into the socket jumpers.

Since the connection is missing I'm going to assume that BIOS will not enable correct WB operation on any 486 chips either. The bigger problem is SiS 496 mobo jumpers allow PCD from chipset (actually through some F gate) to be connected to either PCD input on J17, or CACHE# input on B12. But this means J17 is left unconnected in WB mode, whereas on this mobo it would be always connected to the PCD (now CACHE#), since there is no jumper to break that connection. Would that still work properly? I'm not so sure. In the end I think I'll just accept this particular mobo is not WB-capable for 486 CPUs, the performance difference is small.

EDIT: Well, maybe J17 can be isolated after all. I might have measured the connection with the jumper in place by accident. So I'll try the wire mod at some point but not now, I've already spent too much time on this.

Reply 43 of 60, by Chkcpu

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Hi Deunan,

In my experience, all SiS471 boards support 486WB CPUs. Mine, with a week 27-1994 SiS471 chip, certainly does! 😀
But the challenge of course is to find the correct jumper settings, and often a BIOS update is required as well.

What is your SiS 471 board’s make and model? I may have a few pointers for you.

Cheers, Jan

CPU Identification utility
The Unofficial K6-2+ / K6-III+ page

Reply 44 of 60, by Deunan

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Chkcpu wrote on 2023-07-24, 18:45:

What is your SiS 471 board’s make and model? I may have a few pointers for you.

It's identical to this one: https://theretroweb.com/motherboards/s/qdi-sis471-260-g
The name is what the BIOS displays "SIS471 260 G MAIN BOARD", so basically a no-name. And the jumpers are a proper mess. Some are called Jnn but most are JPnn. Numbers go up to mid-40 and the naming scheme is chaotic. JP41 and JP44 are on pretty much opposite sides of the mobo, diagonally. JP3/JP4 which have something to do with VLB slots (waitstates?) are surrounded by higher number jumpers. Most CPU socket configuration is, more-or-less, around the socket but I really mean around. All sides pretty much. There are even jumpers for the SIMM slots that must be set right to get the sticks recognized properly. 40MHz CPU clock and VLB is pretty much out of question, but at least 33MHz works reasonably stable. SX type CPUs are not stable (something NMI related) on cold mobo, no such issues with DX. In fact it's better to jumper the SX as DX and just avoid using NMI, this way it always boots properly. I think I'm going to leave a standard DX2-66 in there for good, I'm already tired of experimenting with this mobo, and that particular CPU and current jumper settings seem pretty stable. I got 32M SIMM stick with parity properly recognized and working at tight timings, I don't think I need any more headaches related to possible instability with WB mode. And since there is no voltage regulator and I only have one 5V WB-capable CPU I'd rather keep it for experiments on other mobos.

Reply 45 of 60, by Chkcpu

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Yeah, I hear you. Enough time spend on this mobo. 😉

These obscure boards can be a real PITA and 40 plus jumpers is not uncommon on these VLB boards. Even if you have the manual you sometimes need to use a multimeter to check which jumper connects to a certain CPU pin. I did this recently on an UMC498 VLB board to get the (unsupported) Am5x86-133 running in L1 WB mode. It appeared that the documentation didn’t match my board revision…

Cheers, Jan

CPU Identification utility
The Unofficial K6-2+ / K6-III+ page

Reply 46 of 60, by Baoran

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Chkcpu wrote on 2023-07-24, 09:59:
Yes, this is confusing. A possible explanation is that the 80486DX4 jumper settings are for both the regular Intel DX4 as well a […]
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Baoran wrote on 2023-07-23, 18:21:
Chkcpu wrote on 2023-07-23, 16:10:
Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode! The iDX4 is basical […]
Show full quote

Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode!
The iDX4 is basically a L1 Cache WT only CPU. Okay, Intel later made a WB Enhanced DX4 version, but the jumpers for that model are not in this manual.

A way out of this jumper hell is this nice resource:
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm
In the table below the socket diagram, you can see that (except for the P24T) all WB capable 486 CPUs from Intel and AMD use the same pins for the essential L1 WB signals INV (A10), HITM (A12), CACHE (B12), and WB/WT (B13).

The jumper settings for iDX4-WB, Am486DX2-WB, Am486DX4-WB, and Am5x86 are not in the manual. But luckily the settings for the P24D (i486DX2-WB) are, so you can use those for the Am5x86!

The only deviation of course is to keep the CPU Voltage selection on 3.3V!! 😉

Without the JP16 7-8 jumper, the Am5x86 should now run correctly in x3 multiplier and L1 cache WB mode with the v2.3 BIOS. I really hope this works!

Jan

Why JP32 closed turns on WB cache and it is aldo closed in dx4 settings then?

Yes, this is confusing.
A possible explanation is that the 80486DX4 jumper settings are for both the regular Intel DX4 as well as the AMD 486DX4 NV8T. These are both L1 cache WT-only CPUs.

The Am486DX4 NV8T uses pin B13 as CLKMUL, the same pin that the iDX4-WB uses for WB/WT. So JP32 must be closed to get an Am486DX4 NV8T in x3 multiplier mode. This 80486DX4 jumper setting works for the Am486DX4 NV8T and the regular iDX4 because B13 is an INC pin (Internally Not Connected) on the regular iDX4.

The JP16 7-8 jumper setting also works for both DX4 models because it controls pin R17 that is CLKMUL on the iDX4 and INC on the Am486DX4 NV8T.

But the 80486DX4 jumper setting are still missing the required HITM and CACHE signal connections that the P24D settings have. So just try the P24D settings and see where it gets you. 😉

Jan

P24D settings fixed half of the problem. Floppy drive works in WB mode fine as long as multiplier is 3x but stops working in 4x. Turbo button still not working in WB mode even with 3x multiplier but works fine if WT mode with both 3x and 4x multiplier. Or perhaps you could say that it is working too well. Look what happens when I press the turbo button and in WB mode:

P_20230726_015633.jpg
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P_20230726_015633.jpg
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Fair use/fair dealing exception

I think turbo button must be doing something to the cache because if you set "boot up system speed" in bios to "low" it disables the cpu cache even if the cpu cache has been set to enabled in other bios settings. This might be just guessing from my part though.

Reply 47 of 60, by Disruptor

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Baoran wrote on 2023-07-25, 23:16:

P24D settings fixed half of the problem. Floppy drive works in WB mode fine as long as multiplier is 3x but stops working in 4x. Turbo button still not working in WB mode even with 3x multiplier but works fine if WT mode with both 3x and 4x multiplier. Or perhaps you could say that it is working too well. Look what happens when I press the turbo button and in WB mode:

P_20230726_015633.jpg

I think turbo button must be doing something to the cache because if you set "boot up system speed" in bios to "low" it disables the cpu cache even if the cpu cache has been set to enabled in other bios settings. This might be just guessing from my part though.

Sounds like your chipset isn't initialized correctly when your processor is recognized with x4 CPUID. So the BIOS does not initialize WB mode.
Deturbo on a 486 adds waitstates and disables cache(s).

Unless you can try a BIOS with x4 support you may try x3 with 40 or 50 MHz FSB. Remember clock dividers for ISA (/5 or /6) and PCI (2/3 or 1/2) and waitstates (VLB, RAM, L2-cache, memory).

Reply 48 of 60, by Baoran

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Disruptor wrote on 2023-07-26, 00:45:
Sounds like your chipset isn't initialized correctly when your processor is recognized with x4 CPUID. So the BIOS does not initi […]
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Baoran wrote on 2023-07-25, 23:16:

P24D settings fixed half of the problem. Floppy drive works in WB mode fine as long as multiplier is 3x but stops working in 4x. Turbo button still not working in WB mode even with 3x multiplier but works fine if WT mode with both 3x and 4x multiplier. Or perhaps you could say that it is working too well. Look what happens when I press the turbo button and in WB mode:

P_20230726_015633.jpg

I think turbo button must be doing something to the cache because if you set "boot up system speed" in bios to "low" it disables the cpu cache even if the cpu cache has been set to enabled in other bios settings. This might be just guessing from my part though.

Sounds like your chipset isn't initialized correctly when your processor is recognized with x4 CPUID. So the BIOS does not initialize WB mode.
Deturbo on a 486 adds waitstates and disables cache(s).

Unless you can try a BIOS with x4 support you may try x3 with 40 or 50 MHz FSB. Remember clock dividers for ISA (/5 or /6) and PCI (2/3 or 1/2) and waitstates (VLB, RAM, L2-cache, memory).

I removed wait stated before from bios when I was trying to make it faster before so I will try tomorrow to change if they make any difference.

Also I noticed interesting thing. Even if the turbo button is not working properly using keyboard with hotkeys ctrl-alt-minus and ctrl-alt-plus does work properly even with 3x multiplier and in WB cache mode. I have not tried with 4x multiplier because floppy drive is not working then so I did not do many tests.

Reply 49 of 60, by Disruptor

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Baoran wrote on 2023-07-26, 01:51:

I removed wait stated before from bios when I was trying to make it faster before so I will try tomorrow to change if they make any difference.

I meant you need those waitstates when you increase FSB from 33 (100 MHz) to 40 (120 MHz) or 50 (150 MHz).
The lower the FSB frequency the lower the waitstates and vice versa.

Reply 50 of 60, by Baoran

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Disruptor wrote on 2023-07-26, 05:45:
Baoran wrote on 2023-07-26, 01:51:

I removed wait stated before from bios when I was trying to make it faster before so I will try tomorrow to change if they make any difference.

I meant you need those waitstates when you increase FSB from 33 (100 MHz) to 40 (120 MHz) or 50 (150 MHz).
The lower the FSB frequency the lower the waitstates and vice versa.

There is "dram wait states" setting in bios that has settings 0 WS for bus speeds 16-25Mhz, 1 WS for 33-40Mhz and 2 WS for 50-66Mhz it seems and I have set it to "25 Mhz, 0 WS" even though I have been running it at 33mhz bus speed all the time.

Also I have both SRAM burst read cycle and SRAM burst write cycle at lowest setting at 2-1-1-1.

Edit: Well, I tried changing them to "100Mhz, 1WS" and 3-2-2-2, but that did not change anything when it comes to turbo button.

Reply 51 of 60, by Disruptor

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the 25 MHz setting should be fine for 33 MHz

it's getting funny with 40 MHz and 50 MHz
2-1-1-1 SRAM burst is a challenge on 40 MHz (most likely it needs SRAM in 2 banks = 8 chips + TAG), perhaps you need to slow it down to 3-1-1-1 or 2-2-2-2
on 50 MHz it most likely will be a 3-2-2-2 burst

DRAM waitstates are a challenge too at 40 MHz
you have to try the options you have, and on most BIOS you can choose waitstates for read and write separately

run quake and doom test from dosbench suite
and do it with both cold and warm machine

Last edited by Disruptor on 2023-07-28, 08:10. Edited 1 time in total.

Reply 52 of 60, by Baoran

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Disruptor wrote on 2023-07-26, 13:10:
the 25 MHz setting should be fine for 33 MHz […]
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the 25 MHz setting should be fine for 33 MHz

it's getting funny with 40 MHz and 50 MHz
2-1-1-1 SRAM burst is a challenge on 40 MHz (most likely it needs SRAM in 2 banks = 8 chips + TAG), perhaps you need to slow it down to 3-1-1-1 or 2-2-2-2
on 50 MHz it most likely will be a 3-2-2-2 burst

DRAM waitstates are a challenge too at 40 MHz
you have to try the options you have, and on most BIOS you can choose waitstates for read and write separately

run quake and doom test from dosebench suite
and do it with both cold and warm machine

Any chance WB support for 5x86 could be added to the bios so that WB would work with 4x multiplier? Bios already thinks it is a 120Mhz am486dx4-s during post when in using 4x multiplier and 33Mhz bus and does not seem to understand higher frequencies.

Reply 53 of 60, by Chkcpu

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Baoran wrote on 2023-07-26, 14:23:
Disruptor wrote on 2023-07-26, 13:10:
the 25 MHz setting should be fine for 33 MHz […]
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the 25 MHz setting should be fine for 33 MHz

it's getting funny with 40 MHz and 50 MHz
2-1-1-1 SRAM burst is a challenge on 40 MHz (most likely it needs SRAM in 2 banks = 8 chips + TAG), perhaps you need to slow it down to 3-1-1-1 or 2-2-2-2
on 50 MHz it most likely will be a 3-2-2-2 burst

DRAM waitstates are a challenge too at 40 MHz
you have to try the options you have, and on most BIOS you can choose waitstates for read and write separately

run quake and doom test from dosebench suite
and do it with both cold and warm machine

Any chance WB support for 5x86 could be added to the bios so that WB would work with 4x multiplier? Bios already thinks it is a 120Mhz am486dx4-s during post when in using 4x multiplier and 33Mhz bus and does not seem to understand higher frequencies.

Yes, I'm already working on a patched BIOS with proper 5x86 support including the x4 multiplier.
I expect to have it ready in a day or two. 😀

Jan

CPU Identification utility
The Unofficial K6-2+ / K6-III+ page

Reply 54 of 60, by Sphere478

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You are a gift Chkcpu, what would we do without you.

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 55 of 60, by Baoran

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Chkcpu wrote on 2023-07-26, 15:22:
Yes, I'm already working on a patched BIOS with proper 5x86 support including the x4 multiplier. I expect to have it ready in a […]
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Baoran wrote on 2023-07-26, 14:23:
Disruptor wrote on 2023-07-26, 13:10:
the 25 MHz setting should be fine for 33 MHz […]
Show full quote

the 25 MHz setting should be fine for 33 MHz

it's getting funny with 40 MHz and 50 MHz
2-1-1-1 SRAM burst is a challenge on 40 MHz (most likely it needs SRAM in 2 banks = 8 chips + TAG), perhaps you need to slow it down to 3-1-1-1 or 2-2-2-2
on 50 MHz it most likely will be a 3-2-2-2 burst

DRAM waitstates are a challenge too at 40 MHz
you have to try the options you have, and on most BIOS you can choose waitstates for read and write separately

run quake and doom test from dosebench suite
and do it with both cold and warm machine

Any chance WB support for 5x86 could be added to the bios so that WB would work with 4x multiplier? Bios already thinks it is a 120Mhz am486dx4-s during post when in using 4x multiplier and 33Mhz bus and does not seem to understand higher frequencies.

Yes, I'm already working on a patched BIOS with proper 5x86 support including the x4 multiplier.
I expect to have it ready in a day or two. 😀

Jan

Thank you so much. I have a VLB card for it that doesn't really like 40Mhz bus and jumper manual does not mention anything about being able to set wait states for it.

Reply 56 of 60, by Chkcpu

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Baoran wrote on 2023-07-25, 23:16:

P24D settings fixed half of the problem. Floppy drive works in WB mode fine as long as multiplier is 3x but stops working in 4x. Turbo button still not working in WB mode even with 3x multiplier but works fine if WT mode with both 3x and 4x multiplier. Or perhaps you could say that it is working too well.

Hi Baoran,

I’m very pleased to hear the P24D jumper settings did the trick for L1 cache in WB mode! 😀
So now we know the Am5x86 CPU is good, the chipset correctly supports L1 WB, and the automatic WB enable logic in the BIOS works for supported CPUs.

Disruptor wrote on 2023-07-26, 00:45:

Sounds like your chipset isn't initialized correctly when your processor is recognized with x4 CPUID. So the BIOS does not initialize WB mode.

Disruptor is correct. When analyzing the BIOS code, this lack of Am5x86 CPUID support is exactly what I found. So I made a patched BIOS version to fix this and here is the result:

Filename
EXP4045_J1.zip
File size
44.79 KiB
Downloads
30 downloads
File comment
EXP4045 v2.3 patch J.1 BIOS
File license
Public domain

In the zip-file you’ll find a PATCH.TXT file that lists the changes I’ve made to this EXP4045 Rev 2.3 BIOS. I’ve added a - patch J.1 – indication to the BIOS Sign-on message to distinguish the patched BIOS from the original.

Some remarks about this patched EXP4045 BIOS:
While adding Am5x86 and x4 multiplier CPUID support, I found a way to add the proper Am5x86-P75 string as well, so the CPU should be correctly indicated as “Am5x86-P75-S” when run in x4 mode, be it either WT or WB. (In x3 mode, the indication will still be “Enhanced Am486DX4-S” like before.)
I also fixed the FSB calculation for the x4 multiplier mode of both the Am5x86 and Cx5x86, so the automatic RAM and L2 cache timings still work accurately in this mode. This change should also fix the CPU speed indication, although 4x33 will be indicated as 132MHz instead of the more common 133MHz. 😉

You may notice a new “Internal Cache WB/WT” option in the BIOS. Looking at the BIOS code, I believe this option only works for the Pentium Overdrive CPU (P24T) and doesn’t do anything on all other 486WB CPUs like your Am5x86.

Finally, I noticed that this BIOS had the infamous 2GB HDD size display limit bug so I fixed that as well. Drive sizes up to 8GB are now shown correctly. 😀

When you are able to test this BIOS, I’m curious to know how it works.
Happy testing,
Jan

CPU Identification utility
The Unofficial K6-2+ / K6-III+ page

Reply 57 of 60, by Baoran

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Chkcpu wrote on 2023-07-27, 18:35:
Hi Baoran, […]
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Baoran wrote on 2023-07-25, 23:16:

P24D settings fixed half of the problem. Floppy drive works in WB mode fine as long as multiplier is 3x but stops working in 4x. Turbo button still not working in WB mode even with 3x multiplier but works fine if WT mode with both 3x and 4x multiplier. Or perhaps you could say that it is working too well.

Hi Baoran,

I’m very pleased to hear the P24D jumper settings did the trick for L1 cache in WB mode! 😀
So now we know the Am5x86 CPU is good, the chipset correctly supports L1 WB, and the automatic WB enable logic in the BIOS works for supported CPUs.

Disruptor wrote on 2023-07-26, 00:45:

Sounds like your chipset isn't initialized correctly when your processor is recognized with x4 CPUID. So the BIOS does not initialize WB mode.

Disruptor is correct. When analyzing the BIOS code, this lack of Am5x86 CPUID support is exactly what I found. So I made a patched BIOS version to fix this and here is the result:

EXP4045_J1.zip

In the zip-file you’ll find a PATCH.TXT file that lists the changes I’ve made to this EXP4045 Rev 2.3 BIOS. I’ve added a - patch J.1 – indication to the BIOS Sign-on message to distinguish the patched BIOS from the original.

Some remarks about this patched EXP4045 BIOS:
While adding Am5x86 and x4 multiplier CPUID support, I found a way to add the proper Am5x86-P75 string as well, so the CPU should be correctly indicated as “Am5x86-P75-S” when run in x4 mode, be it either WT or WB. (In x3 mode, the indication will still be “Enhanced Am486DX4-S” like before.)
I also fixed the FSB calculation for the x4 multiplier mode of both the Am5x86 and Cx5x86, so the automatic RAM and L2 cache timings still work accurately in this mode. This change should also fix the CPU speed indication, although 4x33 will be indicated as 132MHz instead of the more common 133MHz. 😉

You may notice a new “Internal Cache WB/WT” option in the BIOS. Looking at the BIOS code, I believe this option only works for the Pentium Overdrive CPU (P24T) and doesn’t do anything on all other 486WB CPUs like your Am5x86.

Finally, I noticed that this BIOS had the infamous 2GB HDD size display limit bug so I fixed that as well. Drive sizes up to 8GB are now shown correctly. 😀

When you are able to test this BIOS, I’m curious to know how it works.
Happy testing,
Jan

Thank you for modding the bios.
I have ordered 10 of those eeproms and I have to wait until if/when they arrive before I get to test it. It might take several weeks based on their estimation of how long it takes.

Reply 58 of 60, by mcguli

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Baoran wrote on 2023-07-29, 06:03:
Chkcpu wrote on 2023-07-27, 18:35:
Hi Baoran, […]
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Baoran wrote on 2023-07-25, 23:16:

P24D settings fixed half of the problem. Floppy drive works in WB mode fine as long as multiplier is 3x but stops working in 4x. Turbo button still not working in WB mode even with 3x multiplier but works fine if WT mode with both 3x and 4x multiplier. Or perhaps you could say that it is working too well.

Hi Baoran,

I’m very pleased to hear the P24D jumper settings did the trick for L1 cache in WB mode! 😀
So now we know the Am5x86 CPU is good, the chipset correctly supports L1 WB, and the automatic WB enable logic in the BIOS works for supported CPUs.

Disruptor wrote on 2023-07-26, 00:45:

Sounds like your chipset isn't initialized correctly when your processor is recognized with x4 CPUID. So the BIOS does not initialize WB mode.

Disruptor is correct. When analyzing the BIOS code, this lack of Am5x86 CPUID support is exactly what I found. So I made a patched BIOS version to fix this and here is the result:

EXP4045_J1.zip

In the zip-file you’ll find a PATCH.TXT file that lists the changes I’ve made to this EXP4045 Rev 2.3 BIOS. I’ve added a - patch J.1 – indication to the BIOS Sign-on message to distinguish the patched BIOS from the original.

Some remarks about this patched EXP4045 BIOS:
While adding Am5x86 and x4 multiplier CPUID support, I found a way to add the proper Am5x86-P75 string as well, so the CPU should be correctly indicated as “Am5x86-P75-S” when run in x4 mode, be it either WT or WB. (In x3 mode, the indication will still be “Enhanced Am486DX4-S” like before.)
I also fixed the FSB calculation for the x4 multiplier mode of both the Am5x86 and Cx5x86, so the automatic RAM and L2 cache timings still work accurately in this mode. This change should also fix the CPU speed indication, although 4x33 will be indicated as 132MHz instead of the more common 133MHz. 😉

You may notice a new “Internal Cache WB/WT” option in the BIOS. Looking at the BIOS code, I believe this option only works for the Pentium Overdrive CPU (P24T) and doesn’t do anything on all other 486WB CPUs like your Am5x86.

Finally, I noticed that this BIOS had the infamous 2GB HDD size display limit bug so I fixed that as well. Drive sizes up to 8GB are now shown correctly. 😀

When you are able to test this BIOS, I’m curious to know how it works.
Happy testing,
Jan

Thank you for modding the bios.
I have ordered 10 of those eeproms and I have to wait until if/when they arrive before I get to test it. It might take several weeks based on their estimation of how long it takes.

Hi, I have got a EXP4045 with BIOS 2.2.

This BIOS have 2 problems: hard disk limit to 2GB and y2k bug for year.

I view upper that EXP4045_J1.zip fix 2GB limit but, I will need to buy virgin eprom and a recorder for it, what model of eprom and recorder should I buy for the bios of this board?

Thank you.

Reply 59 of 60, by mkarcher

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mcguli wrote on 2023-10-24, 12:09:

I view upper that EXP4045_J1.zip fix 2GB limit but, I will need to buy virgin eprom and a recorder for it, what model of eprom and recorder should I buy for the bios of this board?

Thank you.

This board uses a 28-pin DIP 64KB EPROM. Those chips are generally named 27C512 with differing vendor prefixes. There is a pin-compatible electrically erasable (flash-like) EEPROM by Winbond called the W27EE512 (earlier revision) or W27C512 (later revision) (the model number looks exactly like the Am27C512 by AMD, but the Winbond chip does not require UV erasure!), which I would recommend over UV-erasable EPROMs for hobby use. A generally recommendable programmer for these kind of chips, both the UV-erasable EPROM as well as the EEPROMs and flash chips is the TL866, but that one is not cheap.