In two words: EDO is mostly supported only by Pentium (Socket 5/7 or later) motherboards with rare exceptions for the best known 486 boards. FPM is supported by ALL motherboards having SIMM slots. Exceptions such as very old 8086-type machines equipped with a SIMM slot, or very dumb Pentium machines are possible but should be extremely rare.
If the model of the chip (but not the latency rating, just type!) ends with 0 (zero), it's FPM (or a vintage simple DRAM with no FPM), but if it ends with 5 (or, any other non-zero digit), it's EDO. That's it.
Some details below.
Let's start from the basics.
Memory can be described in many ways:
1. Form-factor (DIP (dual in-line package) chip, SIP (single in-line package) chip, 30-pin, 72-pin or other xx-pin SIMM (single in-line memory module, both sides are parallel, with via at EACH contact), DIMM (dual in-line memory module, sides are different), So-DIMM.
2. Design type (SRAM/DRAM/ROM, etc)
3. Synchronicity (synchronous/asynchronous)
4. technology/generation within given type (Plain, FPM, EPM, EDO for DRAM)
5. Parity (Parity/Non-parity module)
6. ECC (error correction module, not the same as parity)
There are two general types of ram: SRAM (static) and DRAM (dynamic). The first is also known as Cache and CMOS, the actual bits are stored in kind of FLIP-FLOP transistor circuits and it can hold its contents draining very few current, so it can be backed up with a single battery, but costs a lot. Typical application of SRAM is early hand-held computers like Atari Portfolio, all kinds of battery-driven "non-volatile" RAM cards, BIOS settings (that are stored inside the chipset) and any kind of cache or build-in RAM of microcontrollers. Usually it's DIP-28 or DIP-32 or SOIC-28W chips with names starting with 24 or 62: 24257, 24257, 62512, 62258, 6264, etc.
Unlike SRAM, DRAM has much more simple design and effectively holds the data in capacitors, which discharge is controlled by transistors. This type of memory cell takes a LOT less silicon space, so DRAM chips are cost-effective for high capacity, but in exchange this interface requires a spacial refresh procedure once a several milliseconds, so it should be powered all the time, and also, due to high capacity, it splits the memory addresses into column and row, and this is why it's slower than SRAM: memory controller has to convert linear addresses to column and row addresses.
First generation DRAM chips were able to perform a simple read/write cycle: row address set, strobe, column address set, strobe, R/W, then you get a SINGLE word of memory in terms that the word is a minimal addressable volume of memory: 1 bit, 4 bits, or a whole array of chips, giving a 8/9-bit (30-pin SIMMs), or even 32/36-bit WORDS, each of which has an address and accessed the whole word at once. This kind of memories were typically 21 series DRAM on 8088/8086 era machines. Old chips, like 2164 or 21256 are that rare and vintage type of RAM. Usually even the speed rating is measured not in ns of latency, but in MHz of maximum CPU frequency. (4, 6, 8, 10, 12)
The next generation (41 and 51-series DRAM, later 81-series and other equivalents) had an important improvement: Fast Page Mode (FPM). This mode allowed to define the row address once, then read/write/refresh a whole page (hence the name) of data (literally the entire row) by sequentially strobing only column addresses, which made sequential read faster. Almost all 30-pin SIMMs are FPM. The speed rating measured in ns of /CAS to output latency (IIRC): 50 to 120 ns. Most of FPM (as well as EDO) DRAM chips are SOJ-26 with 2 or 6 absent legs at the middle, as well as SOJ-40 or SOJ-42, used in 2/4-chip SIMM modules or 512K+ VGA cards of ISA/VLB era and early PCI cards like S3 TRIO, CL, etc.
The DRAM we're talking about is Synchronous, in terms that it waits for a specific sequence of address set, /RAS, another address, /CAS signals to transfer the data. Unlike that, Synchronous memory (SDRAM) needs a dedicated CLOCK signal, so it can work in very effective burst modes, transferring sequential data words each clock cycle without need for specific sequence or waits. Most of the time, the SDRAM chips are in SOP packages and the rating is measured in MHz of clock frequency, not ns!
The main problem with this synchronous approach was inevitable latency and need to synchronize it somehow between CPU and FSB clock. The memory controller had to do the following during memory read: get a memory access command from the CPU, translate it to RAS/CAS strobes, wait for the data to appear on the data bus after 60-80 ns, latch it and transfer it back to CPU. The data had to be read before sending the next CAS or RAS/CAS strobes, so there was some time loss and that was the main reason why 386 and 486 motherboards got L2 cache. It was much faster that DRAM and could operate in 1-2 CPU cycles.
So, FPM DRAM was used in all 286, 386 and 486 computer (there were later 486 MB with EDO support but I've never seen one), and all early VGA cards.
The EDO (Extended Data Out) means a single simple idea: it keeps data at the Data bus as long as possible until the very last /CAS is coming in order to request the next word of data. This allows memory controllers to plan data fetching procedures in more optimized way making EDO modules faster in operation. But the problem is that EDO is not backwards-compatible with FPM memory controllers, so old motherboards don't expect memory modules to keep data in data lines after rising the /CAS line back to HIGH state, so they can't support EDO modules, although I never seen the vice-versa situation when you couldn't install FPM modules into a Socket-7 motherboard.
Actually there are techniques for modding EDO modules to emulate behavior of FPM and for the most cases it does work just perfect. The DIY 30-pin SIMM modules by Alexandru Groza are using exactly this technique.
Memory capacity is measured in words, because machine word is a memory volume having specific, single address, but the exact number of BITS in word is determined by the CPU architecture and hance, the DATA bus width.
A typical 30-pin 1MB module consists of 3 chips: 2 chips of 1Mx4 (1 Megaword by 4 bits) and 1Mx1 for parity, so when 1Mx9 is referenced, it's 1 MByte with parity bit.
A typical 72-pin 4MB non-parity module can either consist of two 1Mx16 chips (SOJ-40), which gives 32 Mbits = 4 MBytes with 32-bit words (right, the size of int!) or eight 1Mx4 chips, giving exactly the same 1M words of 32 bits, or 4 MBytes.
And this is the math behind detecting the right memory capacity from photo and datasheet (if you don't remember what each partname means)
Few more notes.
* Not all DIMM modules are SDRAM. There are EDO DRAM DIMM modules. Some of early Socket-7 motherboards do not dupport SDRAM DIMM but support EDORAM DIMM.
* There are 80-pin and 72-pin SIMM modules with ROM and Flash. Usually a character sets for HP printers or memory for Cisco networking equipment. absolutely not compatible with PC.
* Not all modules looking like a 72-pin SIMM are technically SIMMs. I have a pack of server DIMM modules in 72-pin SIMM form-factor, but with actual 144 _different_ contacts and double-width data bus.
* 20pin SOJ-26 chips are usually 256K words x 1 or 4 bits or 1M words x 1 or 4 bits or 4M x 1 bit. This means that 9-chip 30-pin SIMMs can be either 256K or 1M or even 4M depending on the actual chip models.
* 24pin SOJ-26 chips are almost always 4M words x 4 bits, so if you're looking for 4M 30-pin or 16/32M 72-pin, look for 6 legs a side!
* 24pin wide SOJ-26 with 16M words x 1 bit do exist but usually that large memory is made in SOP packages. 16M by 4 bits are always SOP-32 or something like that.
* NOT ALL of 16-chip 72-pin SIMMs are 32 MB. I've seen a bizzare EDO RAM module with 16x AFL NA511740C5D-60J chips with only 2 data bits used in each chip (and it was different set of pins on each side with visually identical chips!), so this module looked like absolutely legit 32MB module but was physically capable of addressing only 16M (4Mwords x 2bits x 16chips = 128 Mbits; divide by 8 = 16 MBytes)
* Once more about the right way to determine FPM and EDO 72-pin modules. latency doesn't count. Datecodes doesn't count. Gold or silver plating doesn't count. Number of chips or chip form-factor doesn't count. Letters doesn't count. Digits in chip models only count and nothing else.
I hope, this will help.
