The SiS 471 datasheet (https://cdn.hackaday.io/files/183453784885315 … asheet_text.pdf, p. 28) doesn't have that as a supported configuration. It would need to allow: 1Mx36, 1Mx36, 1Mx36, 4Mx36.

Are you messing with cutting down cache timings/RAM wait states, and multiple VLB cards? Others have reported the greatest success with one big SIMM anyway rather than filling up the slots with smaller ones like this.

Agree jake ! does not show using 4m+4m+4m+16m. However it does show 4m+4M+16m with bank3 empty (010101) as long as they are single sided/single ranked. My guess on the odd ram reported size is because it is returning a very odd/unsupported config back to bios.
added: only item for 28Mb is 4mb+8mb+8mb+8mb (110111)...

Try double sided sticks

On my 486 the only way I was able to get to 32mb was two double sided 16mb sticks

The address line arrangement of the sticks change a little bit by how many chips are installed and how. So while one 16mb or whatever size mb may work, another may not. You have to find not only the supported size but the supported physical/logical/address chip layout as well

Sphere478 wrote on 2023-08-19, 03:27:

Try double sided sticks

On my 486 the only way I was able to get to 32mb was two double sided 16mb sticks

The address line arrangement of the sticks change a little bit by how many chips are installed and how. So while one 16mb or whatever size mb may work, another may not. You have to find not only the supported size but the supported physical/logical/address chip layout as well

Think that could be part of the issue. He was trying to get 28Mb, not 32Mb. From datasheets 32Mb has more than one possible methods...4x8Mb or 2x16Mb or 2x8mb+1x16Mb. 28Mb has only one.....

It’s possible that so many 4mb sticks just sinply don’t work with available address lines. It might be an error that such a configuration exists

Hello rpocc,

Apart from your memory configuration issue, there also has been a search for a new BIOS for this board. Did you see this thread?
Help me find a newer BIOS for this 486 Motherboard

Further down in this thread I posted an updated 11/28/95-SIS-85C471B/E/G-2C4I9PA0-00 EPox-GXA486SG-Rev-J.1-BIOS.
This BIOS is free from the Year 2094 and 2GB Harddisk display limit bugs, and fully supports the Am5x86 and Cx5x86 CPUs, and Harddisks up to 8GB.

When you are able to try this BIOS on your board, let us know how it works. This BIOS supports the Am5x86-P75 in 4x33 and L1 cache WB mode. If you have this CPU, it would be great if you can test this Rev J.1 BIOS.

Regards, Jan

jakethompson1 wrote on 2023-08-19, 02:17:

The SiS 471 datasheet (https://cdn.hackaday.io/files/183453784885315 … asheet_text.pdf, p. 28) doesn't have that as a supported configuration. It would need to allow: 1Mx36, 1Mx36, 1Mx36, 4Mx36.

Are you messing with cutting down cache timings/RAM wait states, and multiple VLB cards? Others have reported the greatest success with one big SIMM anyway rather than filling up the slots with smaller ones like this.

At this stage I'm just trying using defaults and I can pick from many ISA and VLB cards, so nah, it doesn't depend really on combination of cards or cache/burst/WS settings.

You was right: the 4-4-4-16 combination is not listed as suported in the datasheet, so I tried 4-4-16-16 with known good modules and got my 40 MB working, as well as 16-16-16-16=64M, so probably the slot isn't malfunctioning. By the way, it doesn't matter if I use ECC or non-ECC modules.
However, it doesn't accept 8-8, giving the same 1280 (yes, not 1080 but actually 1280 ) kilobytes and it doesn't really matter which slot combination I'm using for two two-sided 8M modules, but single 8M in Bank 0 works fine with either of available modules. Also, when I try to insert 8M modules into Bank 0 and Bank 2, it gives me 12M but passes the test.

So, I can live with 24M or even 40M configuration but still can't get why I can't reach 48M with 8-8-16-16 combination. I have two 16M non-ECC modules and two ECC which I would like to keep for another machine which doesn't accept non-ECC, so I'm trying everything to get the maximum capacity from what I have.

Chkcpu wrote on 2023-08-19, 16:13:

Hello rpocc, […]
Show full quote

Hello rpocc,

...
Further down in this thread I posted an updated 11/28/95-SIS-85C471B/E/G-2C4I9PA0-00 EPox-GXA486SG-Rev-J.1-BIOS.
...
Regards, Jan

Wow, that's a great news!
Currently I'm using this BIOS:

Award Modular BIOS 4.50G
4DMS-HL3GC AWARD BIOS REV 1.05 01/12/'96
12/07/95-SIS-85C471B/E/G-2C419E30-00

https://mega.nz/file/wXVhhaoQ#3kIFPp1hOYKo7Fp … VtmYD-bkY1FaBJ8

It does support Cache WB but I wasn't able to make it work with 5x86.

Currently I have 2x AMD-X5-133ADW CPUs and can't test neither of those because I don't have a single later board like one based on Sis496. Would be super-cool to run this on my Sis471.

Could you please suggest the right jumper/RA settings for this stone to enable 4x multiplier? AFAIK it requires 3.45 Volts and it seems that my MB only can give 5V or 3.3V using a regulator. From the standard AMD DX4-100 settings I've set the resistor array to RP12 position (5x86), and JP14 to 1-2 as suggested in the table. The position of JP20 doesn't seem to matter.

So far:
I have two 5x86 processors and maybe one of them is fake because they start differently.
One to my surprise has successfully started but recognized as Am486-S at 100 MHz both with your BIOS (which seem to be superior to mine) and my last BIOS.

The other one doesn't start at all. Maybe the first one is actually fake or has smoother voltage tolerance. Or, simply, the second one is dead.

P.S. If this counts, my board has 4x64K+32K cache configuration
P.P.S. I've connected two pins as suggested at the x4mult post by connecting a free pin of J25 with free GND pin of another jumper and it seems that I've got the X4! CPUID in Speedsys shows 04F4 and Y2K bug is shown as present. And yes, now during post it's recognized as 5x86 CPU @ 133 MHz!

rpocc wrote on 2023-08-19, 17:19:

You was right: the 4-4-4-16 combination is not listed as suported in the datasheet, so I tried 4-4-16-16 with known good modules and got my 40 MB working, as well as 16-16-16-16=64M, so probably the slot isn't malfunctioning. By the way, it doesn't matter if I use ECC or non-ECC modules.
However, it doesn't accept 8-8, giving the same 1280 (yes, not 1080 but actually 1280 ) kilobytes and it doesn't really matter which slot combination I'm using for two two-sided 8M modules, but single 8M in Bank 0 works fine with either of available modules. Also, when I try to insert 8M modules into Bank 0 and Bank 2, it gives me 12M but passes the test.

So, I can live with 24M or even 40M configuration but still can't get why I can't reach 48M with 8-8-16-16 combination. I have two 16M non-ECC modules and two ECC which I would like to keep for another machine which doesn't accept non-ECC, so I'm trying everything to get the maximum capacity from what I have.

Hmm 8-8-16-16 is shown in datasheet (111101 2M*36-D 2M*36-D 4M*36-S 4M*36-S = 48MB)
Are the 8Mb simms double sided with 9 chips per side ? Or are they those odd ones with 3 chip per side ? Many boards do not like those type. Also your boards address scheme may have some limitations even though the data sheet says is OK.
There are issues with double sided simms on many older boards. is why 4mb and 16mb nearly always work where 8mb and 32mb sometimes cause issues....

FWIW, I remember when upgrading my DX2/66 back in 1996 or something, from 8 MiB, I bought a 16MiB module, and when running the two together, I had 20 rather than 24 MiB. IIRC, it was a question of the 8MiB stick being double sided and the 16 being single, it set all to single side.

Horun wrote on 2023-08-20, 02:41:

Are the 8Mb simms double sided with 9 chips per side ? Or are they those odd ones with 3 chip per side ?

Not exactly. Mine are with 1Mx16 chips, some non-ECC and some ECC with a pair of additional 256Kx16 chips per side, but I’ve got the idea. So, your suggestion are 16/18 chip 1Mx4 for 8M modules?

rpocc wrote on 2023-08-19, 17:19:

Currently I have 2x AMD-X5-133ADW CPUs and can't test neither of those because I don't have a single later board like one based on Sis496. Would be super-cool to run this on my Sis471.

Could you please suggest the right jumper/RA settings for this stone to enable 4x multiplier? AFAIK it requires 3.45 Volts and it seems that my MB only can give 5V or 3.3V using a regulator. From the standard AMD DX4-100 settings I've set the resistor array to RP12 position (5x86), and JP14 to 1-2 as suggested in the table. The position of JP20 doesn't seem to matter.

P.S. I've connected two pins as suggested at the x4mult post by connecting a free pin of J25 with free GND pin of another jumper and it seems that I've got the X4! CPUID in Speedsys shows 04F4 and Y2K bug is shown as present. And yes, now during post it's recognized as 5x86 CPU @ 133 MHz!

Looking at the EPox GXA486SG manual and settings sheet on TheRetroWeb, I believe these are the correct jumper/RP settings for an Am5x86-P75:
- resistor array on RP12 and RP13 (P24D setting to connect L1 WB protocol signals between CPU and chipset)
- J13 1-2 closed and J14 1-2 closed (this setting enables the correct chipset pins for the AMD/Intel L1 cache WB protocol)
- J32 2-3 closed and J33 1-2 closed (enables CPU power management interface signals)
- J15 open (this enables L1 cache WB mode. Closing this jumper should get you WT mode)
- J16, all open for 3.3V. Although the Am5x86 is rated for 3.45V, it will run on 3.3V as well.
- J17, closed
- J25, you already found how to use it to get a x4 multiplier. 😉

These settings should support the Am5x86 in x4 multiplier and L1 cache WB mode (CPUID Signature 04F4). A successful bootup from a bootable floppy is a good way to test the L1 cache Write-Back interface between CPU-Chipset-BIOS.

Hope these suggestions work,
Jan

Chkcpu wrote on 2023-08-20, 15:04:

Looking at the EPox GXA486SG manual and settings sheet on TheRetroWeb, I believe these are the correct jumper/RP settings for an […]
Show full quote

Looking at the EPox GXA486SG manual and settings sheet on TheRetroWeb, I believe these are the correct jumper/RP settings for an Am5x86-P75:
- resistor array on RP12 and RP13 (P24D setting to connect L1 WB protocol signals between CPU and chipset)
- J13 1-2 closed and J14 1-2 closed (this setting enables the correct chipset pins for the AMD/Intel L1 cache WB protocol)
- J32 2-3 closed and J33 1-2 closed (enables CPU power management interface signals)
- J15 open (this enables L1 cache WB mode. Closing this jumper should get you WT mode)
- J16, all open for 3.3V. Although the Am5x86 is rated for 3.45V, it will run on 3.3V as well.
- J17, closed
- J25, you already found how to use it to get a x4 multiplier. 😉

These settings should support the Am5x86 in x4 multiplier and L1 cache WB mode (CPUID Signature 04F4). A successful bootup from a bootable floppy is a good way to test the L1 cache Write-Back interface between CPU-Chipset-BIOS.

Hope these suggestions work,
Jan

Thanks, Jan, I've tried to apply all listed settings and got it non-starting. I'm not sure why, but it only starts when J32 and J33 are in a state opposite to yours. Still managed to run only one of my 5x86 using all variants. I think the second one is just burnt.

I have dozen of other 286/386/486/Pentium motherboards, so if you're interested in testing BIOSes for other models, PM me for list of my gear.

Right, jumpers J32 and J33 must connect to other signals or CPU pins than I thought. 😉
So the Normal (default) setting of these jumpers do work for the Am5x86. Great.

Thanks for trying out my suggestions,
Jan

Horun wrote on 2023-08-20, 02:41:

Hmm 8-8-16-16 is shown in datasheet (111101 2M*36-D 2M*36-D 4M*36-S 4M*36-S = 48MB)
Are the 8Mb simms double sided with 9 chips per side ? Or are they those odd ones with 3 chip per side ? Many boards do not like those type. Also your boards address scheme may have some limitations even though the data sheet says is OK.
There are issues with double sided simms on many older boards. is why 4mb and 16mb nearly always work where 8mb and 32mb sometimes cause issues....

So, I've got new modules of exactly 2m*36 (8x 1Mx4 and 4x 256Kx4 per side) and these don't work in pair as well, so either datasheet isn't correct or there is an actual hardware problem.

For performance issues, please consider the cacheable area of your motherboard.

Looks like I've got it why it can't mix 8-8-16-16.
The MB is kind of universal, it has 4x30-pin SIMM footprints at the same place where there are 2x72-pin SIMM slots, so it has two SIMM-related jumpers:
1. SIMM 0 and 1 function as BANK0, 1 SS and BANK 0-1 and BANK 2-3 DS.
2. SIMM 2 and 3 (or 4x30-pin) function: BANK0 or BANK 2-3.

So, if a switch the first jumper to the second settings, the motherboards starts to detect two double-sided 8M modules and probably could detect 2x32M modules but at the same time it completely disables two remaining slots. If i do the opposite, it can use all 4 slots but simply doesn't support anything but 4x single-sided modules or one double-sided module. So, despite what datasheet says it seems that there is either an error in the datasheet or a hardware limitation like underimplemented configuration pins. So I think, the case is closed, the MB is fully operational, just a bit limited. Thank you guys for all your input.