The DIL SRAM chip on the board that you can insert into the (empty) socket is the second TAG-RAM. (The 1st TAG chip is already present on the opposite side of the COAST / CELP slot
The 2 onboard cache chips and the 2 chips on the COAST stick are PB-SRAM.
To enable a cacheable area of 512MB RAM you _need_ to populate the 2nd TAG chip on the mainboard with a 16Kx8 12 or 15nS DIL chip and jumper everything correctly.
You also need a 256K COAST module.
If one of the conditions is not met you are restricted to 64 MB cacheable area.

JF_Sebastian wrote on 2023-11-05, 14:19:

Hello colleagues, […]
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Hello colleagues,

First of all, I would like to say that I have really tried to read up. But I am still confused.

Yesterday I got an offer for an "Asus P/I-P55T2P4 Rev 3.10" with SRAM chip socket and slot for a COAST module. I'm very interested in it, but I don't really understand the SRAM upgrade for more cache RAM in the manual.

My questions are:

- Can I get more cacheable RAM with just an SRAM chip in the socket instead of a COAST module? I have read on the Internet about users who have upgraded to 96 MB of cacheable RAM with an SRAM chip. How does this work? The manual says that a cacheable area of more than 64MB is only possible with pipeline burst cache, but only the COAST module has this.

- What good is an SRAM chip if the cacheable area can only be extended with pipeline burst cache, which is only on the COAST modules?

- Do the SRAM chip and a COAST module have different purposes or tasks?

I would be very happy if someone could explain this to me for dummies?

Best regards and have a nice day!
JF

I am confused by your post.
As far as I know Rev. 3.10 does not have the socket for the Coast module, just the solder points. So it has already the full amount of 512kB SRAM.
Are you sure you have Rev. 3.10? What SRAMs are on the board? I mean the 2 big square ones.

Rev. 3.10 was available with and without COAST slot, the revision number denotes the layout revision of the PCB, that is the same in both cases.
I assume TO has one with the CELP socket present.

Hello guys,

first at all thanks for your replies and information. I guess i understand it and i am really interested in buying such COAST-module and TAG-SRAM chip to upgrading it with more then 64MB RAM. Combined with an 233MMX and Voodoo 2 it seems to by a nice build.

Thanks and best regards.
JF

majestyk wrote on 2023-11-05, 17:45:

To enable a cacheable area of 512MB RAM you _need_ to populate the 2nd TAG chip on the mainboard with a 16Kx8 12 or 15nS DIL chip and jumper everything correctly.

This makes a lot of sense, because this chip will be used for 3 extra tag bits, multiplying the cacheable area by 2³ = 8.

majestyk wrote on 2023-11-05, 17:45:

You also need a 256K COAST module. If one of the conditions is not met you are restricted to 64 MB cacheable area.

This condition does not seem to make sense to (but I know there sometimes are limitations that do not seem to make sense at first): Do you happen know why the cache size upgrade from 256KB to 512KB is necessary to lift the 64MB cacheable area limit?

A cacheable area of 512Mb is possible with 256K L cache according to the data sheet:

There are no valid bits listed in cases with 256K L2 and 8K TAG RAMS - if they cannot be stored, this would mean "write through" operation.

majestyk wrote on 2023-11-06, 13:36:

There are no valid bits listed in cases with 256K L2 and 8K TAG RAMS - if they cannot be stored, this would mean "write through" operation.

The concept 8K vs. 16K tag is about the number of cache lines. An 8K tag chip can store information about 8192 cache lines. As a cache line is 32 bytes (also specified in the quoted datasheet), 8192 cache lines are 262144 bytes of cache. If you have 524288 bytes of cache, this is 16384 cache lines, and you thus need a 16K tag. This is unrelated to the amount of data that is stored per cache line.

Furthermore, you must not confuse "valid" bits with "dirty" (aka "modified") bits. A valid bit can exist in both write-back and write-through configurations, and indicates whether a line contains any kind of valid data. The "dirty" / "modified" bit is only meant for write-back cache and indicates whether the data in the cache still needs to be copied back to main memory. Most consumer 486 chipsets use a topology called "always valid". When the BIOS enables the cache, it reads a lot of data, so that all cache lines are filled with valid data. While the cache is enabled, every write to RAM is monitored by the cache, and the cache contents is kept up to date, so that it never enters an "invalid" state. As there is no "invalid" state, the chipset can not invalidate cache contents on execution of the "INVD" or "WBINVD" instruction, so further reads can still be served from the L2 cache.

I don't understand where the "modified" bit is stored. To support a cacheable area of 64MB at 256KB cache size, 8 tag bits are required. There is neither space for a "valid" nor for a "dirty" bit in an 8K x 8 SRAM chip. At 512KB cache size, one less tag bit is required, so to get 64MB cacheable at 512KB cache size, only 7 tag bits are required, so the 8th bit of the 16Kx8 SRAM can be re-purposed as "valid" bit, thus it makes sense the "including valid bit" is only mentioned for 512KB cache. The only idea that comes to my mind is that the 16K dirty bits required for L2WB are integrated in the TXC (the northbridge).

EDIT: The front page of the datasheet specifies: "Integrated Tag/Valid Status Bits for Cost Savings and Performance" - which seems to indicate that there are indeed bits integrated into the TXC. This poses the question why the datasheet talks about "including valid bit" for the 512KB configuration. Possibly the chipset has 16K dirty bits, but only 8K valid bits? As going to 512KB cache frees up one tag bit, the integrated valid bit is only used in 256KB configuration?

mkarcher wrote on 2023-11-06, 11:54:

This makes a lot of sense, because this chip will be used for 3 extra tag bits, multiplying the cacheable area by 2³ = 8. […]
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majestyk wrote on 2023-11-05, 17:45:

To enable a cacheable area of 512MB RAM you _need_ to populate the 2nd TAG chip on the mainboard with a 16Kx8 12 or 15nS DIL chip and jumper everything correctly.

This makes a lot of sense, because this chip will be used for 3 extra tag bits, multiplying the cacheable area by 2³ = 8.

majestyk wrote on 2023-11-05, 17:45:

You also need a 256K COAST module. If one of the conditions is not met you are restricted to 64 MB cacheable area.

This condition does not seem to make sense to (but I know there sometimes are limitations that do not seem to make sense at first): Do you happen know why the cache size upgrade from 256KB to 512KB is necessary to lift the 64MB cacheable area limit?

Thats really interesting! In the manual to the ASUS P55T2P4 is written that up-to 512MB of cacheable RAM is only possible with Pipelined Burst Cache Module which means, no COAST module - no cacheable area bigger than 64MB. See attachment.

Greetings from Germany
JF

majestyk wrote on 2023-11-06, 13:36:

A cacheable area of 512Mb is possible with 256K L cache according to the data sheet: area2.JPG […]
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A cacheable area of 512Mb is possible with 256K L cache according to the data sheet:
area2.JPG

There are no valid bits listed in cases with 256K L2 and 8K TAG RAMS - if they cannot be stored, this would mean "write through" operation.
area1.JPG

Where did you get this information?

JF_Sebastian wrote on 2023-11-10, 01:01:

Thats really interesting! In the manual to the ASUS P55T2P4 is written that up-to 512MB of cacheable RAM is only possible with Pipelined Burst Cache Module which means, no COAST module - no cacheable area bigger than 64MB. See attachment.

That's not how I understand the attachment. The comment is not about a "Pipelined burst cache module", but just about the technology used for caching. The chips soldered to the Asus board are Pipelined Burst cache (PB) chips, too. The Intel 82430HX chipset supports two different kinds of cache memory: Pipelined Burst SRAM (which is used on every HX board I know), and an obscure technology called "DRAM cache" in the 82430HX data sheet. This "DRAM cache" is, AFAIK, a special kind of DRAM with integrated cache. The HX chipset does not support 512MB cacheable area with "DRAM cache" (which I wonder whether it was ever mass produced), only with PB SRAM. The datasheet of the HX chipset explains how to connect PB SRAM to the HX chipset (both the 256KB and the 512KB configuration), but it has no example schematics on how "DRAM cache" is supposed to be wired. If I am correct that "DRAM cache" is part of some kind of obscure SIMMs, it's obvious why there is no "DRAM cache" schematic: You just hook up the SIMM slots as usual, the only special sauce is the kind of memory chips on the SIMMs.

So the "Burst SRAM only" remark in the Asus documentation doesn't mean anything at all: As the chips on the board are already PB SRAM, there is no way to run the chipset in "DRAM Cache" mode, which would not allow 512KB.

mkarcher wrote on 2023-11-10, 07:05:

JF_Sebastian wrote on 2023-11-10, 01:01:

Thats really interesting! In the manual to the ASUS P55T2P4 is written that up-to 512MB of cacheable RAM is only possible with Pipelined Burst Cache Module which means, no COAST module - no cacheable area bigger than 64MB. See attachment.

That's not how I understand the attachment. The comment is not about a "Pipelined burst cache module", but just about the technology used for caching. The chips soldered to the Asus board are Pipelined Burst cache (PB) chips, too. The Intel 82430HX chipset supports two different kinds of cache memory: Pipelined Burst SRAM (which is used on every HX board I know), and an obscure technology called "DRAM cache" in the 82430HX data sheet. This "DRAM cache" is, AFAIK, a special kind of DRAM with integrated cache. The HX chipset does not support 512MB cacheable area with "DRAM cache" (which I wonder whether it was ever mass produced), only with PB SRAM. The datasheet of the HX chipset explains how to connect PB SRAM to the HX chipset (both the 256KB and the 512KB configuration), but it has no example schematics on how "DRAM cache" is supposed to be wired. If I am correct that "DRAM cache" is part of some kind of obscure SIMMs, it's obvious why there is no "DRAM cache" schematic: You just hook up the SIMM slots as usual, the only special sauce is the kind of memory chips on the SIMMs.

So the "Burst SRAM only" remark in the Asus documentation doesn't mean anything at all: As the chips on the board are already PB SRAM, there is no way to run the chipset in "DRAM Cache" mode, which would not allow 512KB.

Ok, then the best way seems to be to buy the right cache SRAM chip on ebay and try it out 😉 I'll report back on the results.

Best regards and have a nice weekend!
JF

Good evening folks,

today i got my COASTt-Modul. Unfortunately it does not work with my P55T2P4. I updated my BIOS up to the latest official version but it did not change anything. Does anyone have any idea why the module is not working on the mainboard or has it working on the own mainboard?

COASt-module:
HP 0960-0944 SMART 256KB L2 cache sync pipeline-burst 160pin DIMM SEC SRAM COASt

Best regards,
JF

JF_Sebastian wrote on 2023-11-18, 16:50:

today i got my COASTt-Modul. Unfortunately it does not work with my P55T2P4. I updated my BIOS up to the latest official version but it did not change anything.

What do you mean by "does not work"? If the system still boots fine but doesn't use 512KB cache instead of 256KB cache, make sure you jumpered JP5. When you upgrade from 256KB to 512KB, the jumper needs to be changed from 1-2 to 2-3.

Cache modules can be finicky, yet another reason to prefer later revisions of the board and/or using a K6-2/3+. I thought I got lucky with the cache module that I bought to use on my PCChips M520 because it initially worked when using a P55C, but when I tried to use it with a K6-3+ 450 it wouldn't work. I initially assumed that it wouldn't work above 66 MHz FSB, but it refused to work at 400 MHz (6x66) as well, so I gave up on it.

In another thread you said you wanted to use a K6-3 450 with this board? If true, then the difference in performance you will see by adding a cache module will be very small, and I've done benchmarks where disabling the motherboard's cache entirely (when using a K6-3+) gave a tiny bit better performance.

Maybe you can find one of the Asus COAST modules?

Repo Man11 wrote on 2023-11-18, 20:55:

Cache modules can be finicky, yet another reason to prefer later revisions of the board and/or using a K6-2/3+. I thought I got lucky with the cache module that I bought to use on my PCChips M520 because it initially worked when using a P55C, but when I tried to use it with a K6-3+ 450 it wouldn't work. I initially assumed that it wouldn't work above 66 MHz FSB, but it refused to work at 400 MHz (6x66) as well, so I gave up on it.

In another thread you said you wanted to use a K6-3 450 with this board? If true, then the difference in performance you will see by adding a cache module will be very small, and I've done benchmarks where disabling the motherboard's cache entirely (when using a K6-3+) gave a tiny bit better performance.

Maybe you can find one of the Asus COAST modules?

Hello Repo Man11,

thx for your reply. I thought a COASt would improve the performance never the less if it's L2 for oldies or with an K6 as L3. But ok, when it does not make a big difference. And hey the COASt does not want to work either way on the MoBo 😉

Best regards,
JF

mkarcher wrote on 2023-11-18, 20:28:

JF_Sebastian wrote on 2023-11-18, 16:50:

today i got my COASTt-Modul. Unfortunately it does not work with my P55T2P4. I updated my BIOS up to the latest official version but it did not change anything.

What do you mean by "does not work"? If the system still boots fine but doesn't use 512KB cache instead of 256KB cache, make sure you jumpered JP5. When you upgrade from 256KB to 512KB, the jumper needs to be changed from 1-2 to 2-3.

The system does not start - it does nothing when the COASt is sticked in.

Best regards,
JF

It seems you are trying to do two things at same time from your posts. Upgrade cachable ram and get a K6-III 450 working.
you should focus on one first and then the other once the first is fixed, depending on the board/bios revision you may not be able to get both working perfectly at the same time...just my opinion,
or am I mis-reading your posts......

JF_Sebastian wrote on 2023-11-19, 03:26:

The system does not start - it does nothing when the COASt is sticked in. […]
Show full quote

mkarcher wrote on 2023-11-18, 20:28:

JF_Sebastian wrote on 2023-11-18, 16:50:

today i got my COASTt-Modul. Unfortunately it does not work with my P55T2P4. I updated my BIOS up to the latest official version but it did not change anything.

What do you mean by "does not work"? If the system still boots fine but doesn't use 512KB cache instead of 256KB cache, make sure you jumpered JP5. When you upgrade from 256KB to 512KB, the jumper needs to be changed from 1-2 to 2-3.

The system does not start - it does nothing when the COASt is sticked in.

Best regards,
JF

I agree with Horun and I am a bit confused.
Why do you buy a COAST module when you need a tag RAM?

Horun wrote on 2023-11-19, 07:12:

It seems you are trying to do two things at same time from your posts. Upgrade cachable ram and get a K6-III 450 working.
you should focus on one first and then the other once the first is fixed, depending on the board/bios revision you may not be able to get both working perfectly at the same time...just my opinion,
or am I mis-reading your posts......

Hello,

first at all, you 're right. Focusing on both things is not practible. The point is that i first wanted to upgrade the MoBo with the COASt when i had my P200MMX running on it. But then i got an offer for the K6-III and i thought combining both to have a fast CPU with internal L2 and the COASt as L3 would be a good idea. But nevertheless i focus to get the K6-III running.

@coffeeone
If the COASt module had worked with my P200MMX, I would have bought a tag RAM. The cache was more important to me than the cacheable area, and the previous posts of mine are based on the general question of how the cacheable area and cache upgrade work on the P55T2P4.

Thank you very much for your answers, ideas and criticism, and I am sorry if my posts and ideas are sometimes confusing for others.
JF