Hi,

has anyone taken a closer look at the internal workings of the "CPU SOFT MENU" mechanism on Socket 7 / Abit boards yet?
From what I can tell, it looks like my board (Abit AB-SM5) has a Lattice CPLD (ispGDS14), with the programming pins connected to GPIOs on the Ali5123 chipset.

This all sounds pretty interesting (especially in regards to K6-2/3+ mods/usage on old (non-super) Socket 7) boards.
Has anyone already reverse-engineered/looked at the BIOS routines responsible for handling this? Was this an Abit-specific addition?

so long
Manawyrm