I'm setting up a DECpc LP. It has a OPTi 496 chipset and I was able to find only one UMB driver for it, The Last Byte Memory Manager, but I don't like it that much (I also use it on my 286 with HT12 chipset) and on this DECpc it has a problem: CTRL+ALT+DEL locks the system and reset button must be pressed.

But one of the UMB drivers, HiRAM 1.9a, was very promising. It did not support OPTi496 but supports OPTi493 and very few other chipsets. But the most interesting thing was that those were scripts and it looked quite easy to add support for new chipsets. And I did just that, made a script for OPTi496 and HiRAM seems to work without any issues at all on MS-DOS 7.1 even though HiRAM is from 1993.

One problem is that some of the documentation is only in German but most is in English and google translate helped with what little else was needed.

Scripts are text files with .SCR extension. You use MAKHISET.EXE to convert one to HISET.SYS. For example to convert OPTI496.SCR you would write "makhiset opti496" to command prompt. Note that the .scr extension must not be specified. After HISET.SYS is build, you need to load it in config.sys followed by hiram.exe and himem.sys. Then you can load other devices necessary.
Here is an example:

1DOS=HIGH,UMB
2DEVICE=C:\HIRAM\HISET.SYS
3DEVICE=C:\HIRAM\HIRAM.EXE
4DEVICEHIGH=C:\DOS\HIMEM.SYS

That looks simpler than with many other UMB drivers because you don't have to specify the memory addresses at config.sys since they are in the script file. Lets take a look at script file for OPTI496 that I made (I started by editing the OPTI493.SRC that came with HiRAM).

1; ╔═══════════════════════════════════════════════╗
2; ║  Script-File for MakHiSET			  ║
3; ╠═══════════════════════════════════════════════╣
4; ║  Chipset: OPTi  82C496			  ║
5; ╠═══════════════════════════════════════════════╣
6; ║  Enable UMBs for D000-EFFFh                   ║
7; ║  C800h-CFFFh must stay write protected due to ║
8; ║  chipset limitation.                          ║
9; ╠═══════════════════════════════════════════════╣
10; ║ (C) 2022 by aitotat                           ║
11; ╚═══════════════════════════════════════════════╝
12
13;	Driver start message
14MESSAGE		=	OPTi 496, UMBs D000h-EFFFh
15
16; Disable NMI during chipset programming
17NMI		=	OFF
18
19;	Index and Data ports to program Opti 496 chipset
20INDEXPORT	=	22h
21DATAPORT	=	24h
22
23; Write Protect C000h - EFFFh disable
24INDEX		=	32h
25DATA		=	x11xx001b
26;			│││││││└Write protect C000h-CFFFh
27;			││││││└Write protect D000h-DFFFh
28;			│││││└Write protect E000h-EFFFh
29;			││││└Copy enable C000h-EFFFh
30;			│││└Enable (shadow) RAM at C000h-CFFFh
31;			││└Enable (shadow) RAM at D000h-DFFFh
32;			│└Enable (shadow) RAM at E000h-EFFFh
33;			└F000h-FFFFh 0=Enable shadow & write protect, 1=Read&writes to ROM
34
35
36;	Segments D000h - EFFFh Shadow RAM enable
37INDEX		=	33h
38DATA		=	11111111b
39;			│││││││└D000h	\
40;			││││││└D400h	 \
41;			│││││└D800h	  \
42;			││││└DC00h	   \ 0=disable
43;			│││└E000h	   / 1=enable
44;			││└E400h	  /
45;			│└E800h		 /
46;			└EC00h		/
47
48;	Segments C000h - CFFFh Shadow RAM enable
49INDEX		=	34h
50DATA		=	xxxxxx01b
51;			│││││││└Video BIOS area non-cacheable
52;			││││││└ROM F000-FFFFh Write Enable
53;			│││││└Reserved
54;			││││└Reserved
55;			│││└C000h	\
56;			││└C400h	 \ 0=disable
57;			│└C800h		 / 1=enable
58;			└CC00h		/
59
60; This tells HIRAM.EXE where UMB RAM is now available

61RAMINIT		=	D000h - EFFFh
62
63; Chipset programmed, enable NMI
64NMI		=	ON

No programming is needed but you need datasheet for the chipset and you need to find control ports and indentify registers involving shadow RAM. Index port is used to select chipset register. Once it is selected the data port is used to write data to or read data from that selected registers. These two ports must be specified in the script file but then makhiset.exe handles the rest. For OPTi496 those port are:

It should not be too hard to identify the shadow RAM registers. There should not be too many. There are three registers on OPTi496 but we really need just two of them. But I included the third one as well (34h).

I won't explain real mode addressing here or PC memory map expect that VGA BIOS is usually 32k and always at segment C000h. So first segment for next ROM would be at C800h. System BIOS starts from F000h segment so our ROMs and UMBs must be within C800h - EFFFh. In this system we have 8k build of XTIDE Universal BIOS at segment C800h (-C9FFh). So that leaves CA00h-EFFFh available for UMBs.

In the script file INDEXPORT=22h tells the address of index port and DATAPORT=24h tells that data port is port 24h. First chipset register we need to modify is register 32h. We select it with INDEX=32h and configure it with DATA=xxxxxxxxb. So every bit needs to be configured to 0 or 1 or x. X means no change.

We should modify the registers so that we do not override the actual shadow ram settings configured in BIOS setup. We just want to write enable the unused areas so they can be used as UMBs. The first register 32h shows one limitation about this chipset. We can only write enable 64k blocks of RAM event though there is much finer control for shadowing ROMs. Since we always have VGA BIOS at C000h, we must always write protect whole C000-CFFFh. So only D000h-EFFFh are available as UMBs. So having XTIDE Universal BIOS at C800h did not limit our UMBs at all! In fact, we could have total of 32k of ROMs in addition to VGA BIOS and we could still use all the UMBs this chipsets can provide. This shows the importance to properly set the expansion ROM addresses. Start to place them after VGA BIOS and do not leave gaps.

But how to modify register 32h? We set bits 6 and 5 to enable shadow RAM for 64k segments E000h and D000h. Actually it is (UMB) RAM now since we have no ROMs to shadow there. Then we need to clear bits 2 and 3 to write enable those segments. Everything else should be left to x (unchanged) but I set bit 0 to 1 to notify our VGA BIOS needs to be write protected.

Register 33h is easy. We set every bit to 1 to enable those same memory areas we just did at register 32h. Only here we do it in finer 16k steps (for actual shadowing purposes).

And last register, 34h, could be left unmodified because it simply have controls for Cxxxh and F000h-FFFFh that we cannot use as UMBs anyway. But I made sure main BIOS is write protected (bit 1 set to 0) and I also set bit 0 because this system does not have video bios cacheable setting at BIOS setup. Yes, nothing prevents to modify other, UMB unrelated, chipset registers as well! I could, for example, modify memory timings since this system does not have those settings in BIOS setup.

Finally in the script file there is RAMINIT=D000h-EFFFh. It tells where we enabled the UMBs so the driver can use them.

When I have time, I'm going to try making a script for Headland HT12 so I would not have to use TLB memory manager. I'll also make a script for Headland Shasta since I haven't found any UMB driver for it.