Today I was implementing things for mixer locking and dual OPL2 simulation... aand then at the end I press compile button and I'm greeted with the error that design won't fit...
I have some things to try but I may not be able to bring the extra stuff into the mix unfortunately 😒
EDIT: After some struggling, I have managed to make mixer locking and dual OPL2 simulation both fit into the design !
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This CPLD is quite filled up, all the pins are used, 75% of the logic elements are used and close to all the interconnect resources are used. The latter are what gave me all teh headache, I had to shuffle things around and in the end also cut down a few things to a smaller size and then after lot of trying the compiler actually managed to get a fit. Simulations seem to indicate things should work so the coming steps are to flash the CPLD and add support to the new spec in SETYMF, write some test code to verify things work and then I can get to a point where I can call the hardware finished ~
Hopefully I won't have trouble getting matched levels between YMF71x internal OPL3 and one in YMF704/721. They both go into the same input on YMF71x and in worst case I can adjust gain on YMF721 DAC to get a match, hopefully without needing some strange value resistor 🤣
Mixer locking prevents games from issuing a reset to the mixer (and with it make all levels go to shit) and change to master volume when enabled, YMF71x needs it to be at "1" or volume range on other things is not full. SBDAC, Line, CD, FM+WB+MIDI levels can be locked separately when locking is enabled. This should cover all the bases ~