Reply 2061 of 2390, by matze79
Reply 2062 of 2390, by shock__
Reply 2063 of 2390, by Anterag
Amazing! Good job! Is the project still going?
Reply 2064 of 2390, by shock__
Absolutely ... while I'm slowly getting the feeling that my pace for the project is a bit slow, it's going nicely from a technical standpoint 😀
Just ordered some straight SIMM slots for testing.
Also: All slots for the RC run are taken.
Reply 2065 of 2390, by matze79
Reply 2066 of 2390, by shock__
Reply 2067 of 2390, by matze79
That would be nice!!
I still did not figure out why the ROM last time did not work..
they where flashed with right contents.
Maybe it had todo with the defective ultrasound chip ? 😁
I will retry this time 😀
Reply 2068 of 2390, by 640K!enough
I don't remember if we discussed this before; what were the symptoms of the ROM not working? What version of IWINIT did you have installed? Did you get any "Found ROM chip" messages when running iwinit -v?
Usually, as long as the ROM is reliable enough to read the header and verify the checksum, it will configure the registers for ROM support. It doesn't do any other validation of the ROM data, though you may get garbage/noise when trying to play MIDI files.
Reply 2069 of 2390, by matze79
Reply 2070 of 2390, by shock__
Just generated the gerbers ... I'll sleep over them for the night and then send them off to fabrication 😀
I really hope the drills for the alternative SIMM slots are acceptable to them ... otherwise I might have to look into the generation of slots in eagle.
Transition Prototype 02 -> RC 01
! uncrammed C717, C718, C721, C725
+ added C14 (100nF) to CFILT according to datasheet
! added support for non-PnP mode (3 way pads for R11)
+ added support for straight 72pin SIMM connects (additional drills)
! cleaned up RA20/RA21 configuration (JP4 -> R12, JP5 -> R13A, R13B, R13C)
! integrated X3 into the footprint of U31 (as U31EX)
- removed X3
! renamed X1 and X2 to ISA8 and ISA16 to make their purpose clearer
! renamed JPx to Jx
! renamed gameport/audio connectors to X0-X3
! changed silkscreen explainations to reflect the new naming scheme
- removed support for SOJ sockets for U0/U1
+ Added header "ESP" for potential SPDIF daughterboard
Reply 2071 of 2390, by hard1k
Reply 2072 of 2390, by matze79
Reply 2073 of 2390, by Rawit
Reply 2074 of 2390, by Synoptic
Looks good !
Reply 2075 of 2390, by Sev80
I just got back from business travel and saw the prototype run. I'm probably too late, arent I?
Reply 2076 of 2390, by shock__
Reply 2077 of 2390, by foey
Yup, I'm afraid so.
But worry not, the full run is planned for the near future and there'll be a considerable timespan before anyone might possibly end up on a catch-up run.
Same - registering interest for the next run 😀
Cyrix Instead Build, 6x86 166+ | 32mb SD | 4mb S3 Virge DX | Creative AWE64 | Win95
ATC-S PIII Tualatin Win9x Build :- ATC-S PIII Coppermine Win9x Build Log [WIP] **Photo Heavy**
Reply 2078 of 2390, by root42
Reply 2079 of 2390, by shock__
Same here. Would love a kit, since I like soldering, if possible.
Just for future reference, there won't be kits from my side. You'll have to source parts yourself or someone from the community has to offer them (apart from the InterWave IC which comes presoldered with every board).
There are only very minor changes to the bill of materials from Prototype Run #2 (I think 1 additional 10k resistor + the optional ESP header) - I'll update the documentation in time before the PCBs get sent out.