AFAIK there's a bunch of differences between the NCR8496 and PSSJ, vs the SN76489/89A/96, but it boils down to a few things, I believe:
1. The Noise channel LFSR is significantly different; on SN76489/89A/96/etc the LFSR (assuming a leftward-shifting Fibonacci LFSR where bit 0 is the rightmost bit, where the new bit gets shifted into on the next clock) has feedback taps on bits D and E, output tapped from E, XOR function. The NCR8496 and PSSJ, the LFSR has feedback taps on bits A and E, output tapped from E, XNOR function.
2. The Noise LFSR on the TI chips is reset on any write to register 6, regardless of what is written and what the contents of register 6 were. On the NCR8496 and PSSJ, writing to register 6 only resets the LFSR if the value of bit 5 (the periodic vs white noise select) changed vs the previous register contents.
3. Writing to registers which do not have a 'second half' (registers 1, 3, 5, 6, 7) with bit 7 cleared on the NCR8496 and PSSJ does absolutely nothing, while doing so on the TI chips causes the low 4 bits written to 'mirror' to the 4 bits of the first half of those registers. (For register 6, writing to the second half on TI chips also resets the LFSR, like a normal register 6 write would.) This 'writes with bit 7 cleared do nothing on NCR/PSSJ' fact still needs hardware testing to verify its behavior exactly, and whether it applies to all 5 of those registers or just some of them.
There may still be other differences yet to be noticed.
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