640K!enough wrote:Scali wrote:Writes to the OPL2 registers are extremely slow.
After you write to the address port, you need to wait for 3.3 microseconds, and […]
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Writes to the OPL2 registers are extremely slow.
After you write to the address port, you need to wait for 3.3 microseconds, and after you write to the data port, you need to wait for 23 microseconds.
Writing to the printer port is much faster than that, so I think it should be possible to 'hide' the extra writes in the delays required between writes to the OPL2 chip, so you get it 'for free'.
(The delays are usually done by performing 6 IO reads (in al, dx) after an address write, and 35 IO reads after a data write. You could simply remove/replace some with the LPT code).
I wasn't aware you could do that. I was under the impression that the delay began once either WR# or CS# were de-asserted, for a write. That would mean that you had to write to the LPT control port at least twice, plus the data port once before starting the delay. Am I missing something?
Some of the delays may be embedded, but not all. Certainly address setup time can be done before controlling the CS#/WR# active.
It is not completely clear if the requirement is from end of write to end of write, of from end of write to start of write.
However, It should be easy to test how little delay is necessary before things start to go wrong.
I easily managed to get some screeching sounds from OPL2LPT plug as I initially thought it would be slow enough without delays.
So it works exactly like handled too fast when sitting on a ISA bus. With proper delays my player worked fine.
And, it should be easy to test the completely perverse case of starting the data write cycle just after address is written, but terminate it after enough delay.
Same thing for the other case as well, after data write you can start new register address write cycle before the chip is ready but terminate it after enough delay.
I would think that it won't work though, at least it won't if the register address and register data are stored in a latch from the bus. A latch would be sensitive to low level of WR#/CS#, not edge sensitive to rising edge of CS#/WR# like a flip-flop would be. So updating the latch contents during an internal write operation would corrupt the operation of course.
So I would interpret that it means clock cycles between writes. So a certain delay between the cycles, meaning, no matter how lengthy the bus cycles are, it's from end of operation to start of next operation. I could be wrong though, but at least OPL4 datasheet says that after address is written, a certain delay of clock cycles is necessary before next read or write cycle, and after data write, certain delay is necessary before next address or data write cycle. So delays between the write bus cycles.
I think I once counted this, if the OPL chip requires 12/82 clock cycle delays, that's approximately 3.35/23 microseconds, and ISA bus IO cycles assumed being about 660ns, it really is 6 and 35 IO cycles of delay. That's why on faster buses there is need for extra IO wait states.