Scali wrote on 2023-05-17, 13:32:

IRQ2 can't be used on ATs because of the cascading setup of the second PIC

What exactly happens when a card using IRQ 2 is installed in an AT ?
I know that it's serviced as IRQ 9, and supporting IRQ 9 requires the software to be AT-aware.

But what about pre-AT software?
Anything that handles IRQ 2 the PC/XT way, is doomed to fail, right?

Were there any known problems related to that?
I suspect not, as the first popular card using IRQ 2 was EGA, released about the same time as the AT.

Grzyb wrote on 2023-05-17, 14:18:

[..]
Were there any known problems related to that?
I suspect not, as the first popular card using IRQ 2 was EGA, released about the same time as the AT.

IRQ2 for EGA/VGA rarely used in practice or required. Most VGAs had a jumper set with IRQ2 being disabled.
We talked about the vertical retrace interrupt years ago, I vaguely remember.

Grzyb wrote on 2023-05-17, 14:18:

What exactly happens when a card using IRQ 2 is installed in an AT ? I know that it's serviced as IRQ 9, and supporting IRQ 9 re […]
Show full quote

What exactly happens when a card using IRQ 2 is installed in an AT ?
I know that it's serviced as IRQ 9, and supporting IRQ 9 requires the software to be AT-aware.

But what about pre-AT software?
Anything that handles IRQ 2 the PC/XT way, is doomed to fail, right?

Not necessarily, but it can be tricky.
The way it should work is that the pin for IRQ2 on the ISA bus is now connected to IRQ9 on the second PIC.
The second PIC is configured as 'cascaded', which means that it sends an interrupt to the first PIC (connected to IRQ2).
Only the first PIC is actually connected to the interrupt line of the CPU, so the first PIC will signal that there is an interrupt.
On x86 you can have up to 256 interrupts. The PIC will send an interrupt number along with the interrupt signal. Each PIC has 8 inputs, and the interrupt number is a base value + input.
For the first PIC, the base is set to 0x08, so IRQ0 is actually INT 8, IRQ1 is INT 9 etc.
For the second PIC, the base is set to 0x70, so IRQ8 is INT 70, IRQ9 is INT 0x71 etc.

So, when an ISA card generates what it think is an IRQ2, it is actually signaling an IRQ9 on an AT.
This will execute the handler at interrupt vector 0x71.

In cascaded mode, both PICs need to be sent an End-of-Interrupt (EOI) signal.

By default, an AT BIOS will have an INT 0x71 handler which simply sends an EOI to the second PIC and calls the INT 0x10 handler (the original IRQ2 handler).
This handler should normally include an EOI for the first PIC, so this should work the same as on an XT.

But of course this can all go very wrong if somehow the original INT 0x71 handler is overwritten, the second PIC is masked, or gets an interrupt that does not receive an EOI, so it remains dead-in-the-water, if the base offset of 0x70 for the second PIC gets overwritten etc etc.

So yea, IRQ2 *can* work on an AT, but when software tries to take too much control of the system, it is easy to break the default backward compatibility layer.

Scali wrote on 2023-05-17, 13:32:

Grzyb wrote on 2023-05-17, 12:39:

This manual - https://www.manualslib.com/manual/1802842/Cre … 20Blaster%20Pro - states that "IBM 286, 386, 486, or 100% compatibles" are required.

Yea, but that's the new-style manual (same as SB16), apparently from 1994, so that is probably bundled with a card that was configured as IRQ5 anyway.
I wonder if it has always been like that. As I say, I have an old card, that was IRQ7, and the old-style manual and box.

I checked my manual, which is dated Feb 1992, and it says basically the same, AT or higher required, and EGA or VGA, and a HDD with 2.5 MB free.
So apparently they've never promoted the fact that it can work in an XT.