Please remember that there is a slot count limitations to the VLB.
A general rule is:
50 MHz - 0 slots
40 MHz - 1 slot
33 MHz - 2 slots
25 MHz - 3 slots
If you have more slots you may have luck or stability problems.

So you may run that Cirrus chip properly at 50 MHz, when it is onboard and there are no VLB slots.

Disruptor wrote on 2023-09-29, 11:25:

Please remember that there is a slot count limitations to the VLB. A general rule is: 50 MHz - 0 slots 40 MHz - 1 slot 33 MHz - […]
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Please remember that there is a slot count limitations to the VLB.
A general rule is:
50 MHz - 0 slots
40 MHz - 1 slot
33 MHz - 2 slots
25 MHz - 3 slots
If you have more slots you may have luck or stability problems.

So you may run that Cirrus chip properly at 50 MHz, when it is onboard and there are no VLB slots.

oooouch!

Another (quasi)bluff from manufacturers' hyped claims!

Like saying:

This car can run at 450 KM/h

not-mentioned condition: Provided the moon falls towards the Earth in a vector such that you find the moon in front of you and it adds up its gravitational pull to your car

aries-mu wrote on 2023-09-29, 10:51:

every Cirrus Logic GD542x VL-Bus graphic card works with: […]
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every Cirrus Logic GD542x VL-Bus graphic card works with:

FSB @ 50 MHz
0 wait states

The sheet is clear:
http://www.elemar.pl/PDF/CL-GD5422.pdf

That's not how data sheets work. The chip can work at 50MHz FSB, and the chip can work at 0 wait states. The "banner specs" do not necessarily mean that you can get both of these properties at the same time. It wouldn't surprise me at all if "0WS" would only apply to the 12.5MHz ISA mode, and VL mode always requires 1 wait-state at least. You would need to read the full data sheet to find out whether there is support for 0WS at the local bus. I'd guess it's no coincidence that the timing example for a VL cycle on page 3-78 shows a 1WS cycle...

I checked the more detailed documentation: The actual VL wait states are configurable, you need to get the technical reference manual to get the details. On 386/486/VESA local bus, the GD5424-GD5428 can run at 1 to 4 WS, and the GD5429 can run at 0 to 3WS. The data sheet requires that "(wait states+1) / bus clock > 3 / memory clock + 2ns". At the maximum permitted memory clock for the GD5429, which is 60MHz, the right-hand side is 52ns, so at 0WS, the maximum bus clock is slightly below 20MHz, at 1WS, you may go up to 38MHz, and at 2WS, the maximum bus clock of 50MHz is achievable. On earlier chips, the maximum memory clock is 50MHz, so the right hand side is 62ns. The permitted bus clocks thus are 32MHz at 1WS, 48MHz at 2WS, and 50MHz at 3WS.

The ISA memory write specification on page 3-61 specifies that the SMEMW pin needs to be high for at least 3 cycles of the memory clock and low for at least 3 cycles of the memory clock. So you may run one ISA write cycle withing 6 memory clock cycles. As an ISA 0WS write cycle takes 2 bus clocks, this means to get ISA to run at 0WS the memory clock is required to be at least 3 times the ISA clock. And indeed, this is possible: The default memory clock is 40-50MHz, so 0WS at 12.5MHz is possible.

aries-mu wrote on 2023-09-29, 11:31:

Like saying:

This car can run at 450 KM/h

not-mentioned condition: Provided the moon falls towards the Earth in a vector such that you find the moon in front of you and it adds up its gravitational pull to your car

That comparison is not entirely fair. It's more like looking at a SUV data sheet. It might say: Maximum climb angle 30° and maximum speed 180km/h. That does not mean the car can go at 180km/h while climbing up a 30° slope.

mkarcher wrote on 2023-09-29, 19:34:

That's not how data sheets work. The chip can work at 50MHz FSB, and the chip can work at 0 wait states. The "banner specs" do n […]
Show full quote

That's not how data sheets work. The chip can work at 50MHz FSB, and the chip can work at 0 wait states. The "banner specs" do not necessarily mean that you can get both of these properties at the same time. It wouldn't surprise me at all if "0WS" would only apply to the 12.5MHz ISA mode, and VL mode always requires 1 wait-state at least. You would need to read the full data sheet to find out whether there is support for 0WS at the local bus. I'd guess it's no coincidence that the timing example for a VL cycle on page 3-78 shows a 1WS cycle...

I checked the more detailed documentation: The actual VL wait states are configurable, you need to get the technical reference manual to get the details. On 386/486/VESA local bus, the GD5424-GD5428 can run at 1 to 4 WS, and the GD5429 can run at 0 to 3WS. The data sheet requires that "(wait states+1) / bus clock > 3 / memory clock + 2ns". At the maximum permitted memory clock for the GD5429, which is 60MHz, the right-hand side is 52ns, so at 0WS, the maximum bus clock is slightly below 20MHz, at 1WS, you may go up to 38MHz, and at 2WS, the maximum bus clock of 50MHz is achievable. On earlier chips, the maximum memory clock is 50MHz, so the right hand side is 62ns. The permitted bus clocks thus are 32MHz at 1WS, 48MHz at 2WS, and 50MHz at 3WS.

The ISA memory write specification on page 3-61 specifies that the SMEMW pin needs to be high for at least 3 cycles of the memory clock and low for at least 3 cycles of the memory clock. So you may run one ISA write cycle withing 6 memory clock cycles. As an ISA 0WS write cycle takes 2 bus clocks, this means to get ISA to run at 0WS the memory clock is required to be at least 3 times the ISA clock. And indeed, this is possible: The default memory clock is 40-50MHz, so 0WS at 12.5MHz is possible.

aries-mu wrote on 2023-09-29, 11:31:

Like saying:

This car can run at 450 KM/h

not-mentioned condition: Provided the moon falls towards the Earth in a vector such that you find the moon in front of you and it adds up its gravitational pull to your car

That comparison is not entirely fair. It's more like looking at a SUV data sheet. It might say: Maximum climb angle 30° and maximum speed 180km/h. That does not mean the car can go at 180km/h while climbing up a 30° slope.

Wow! Very detailed, thanks!
good points