I've improved the 80286 protected mode a lot the last week. I've tried running the IBM AT BIOS with it, but eventually (before even showing anything or initializing the video adapter), it crashes with a HLT instruction with the Interrupt flag being 0(meaning it will stop doing anything because there's no coprocessor(x87 FPU) making it resume, nor any hardware can wake it up(since the interrupt flag is 0).
I see that the CMOS is written, eventually receiving the values into the status register reaches 0, 1 etc. until it reaches 0x80, then 0x00. I also see a little bit of output to the 0x3DX port range(VGA graphics card).
Anyone knows why the BIOS terminates itself and enters an infinite loop?
The entire core is built, so that each module (8086, 80186, 80286, 80386, 80486, Pentium) only supplies the new instruction opcodes that are added each processor. So the 80286 in this case, uses the 80286, 80186(NEC V30) and 8086 instruction core for it's full instruction set.
Anyone can see why the IBM AT BIOS crashes with the current instruction set? I know that the hardware should all be emulated correctly (The Turbo XT BIOS works without problems on the NEC V30(186) core. The only addition the 286 adds is protected mode with a few new instructions(besides a wider address bus with 24-bits instead of 20 bits address space)?
Edit: I've added a simple port 80h (Diagnostics port) output to the Settings menu. It displays the code 08h? Does this mean there's a problem with my DMA Page register emulation?
Last edited by superfury on 2016-10-24, 17:01. Edited 8 times in total.
1 MOV AL,08H ; <><><><><><><><><><><><> 2 OUT MFG_PORT,AL ; <><> CHECKPOINT 08 <><> 3 SUB AL,AL 4 MOV DX,DMA_ PAGE 5 MOV CX,0FFA ; DO ALL DATA PATTERNS 6C22A: OUT DX,AL 7 INC DX 8 INC AL 9 CMP DX,8FH ; TEST DMA PAGES 81 THROUGH 8EH 10 JNZ C22A 11 XCHG AH,AL ; SAVE CURRENT DATA PATTERN 12 DEC AH ; CHECK LAST WRITTEN 13 DEC DX 14C22B: SUB AL,AL ; CHANGE DATA BEFORE READ 15 IN AL,DX 16 CMP AL,AH ; DATA AS WRITTEN? 17 JNZ C26 ; GO ERROR HALT IF NOT 18 DEC AH 19 DEC DX 20 CMP DX,MFG_PORT ; CONTINUE TILL PORT 80 21 JNZ C22B 22 INC AH ; NEXT PATTERN TO RIPPLE 23 MOV AL,AH 24 LOOP C22A 25 26;----- TEST LAST DMA PAGE REGISTER (USED FOR ADDRESS LINES DURING REFRESH) 27 MOV AL,0CCH ; WRITE AN CC TO PAGE REGISTERS 28C22: MOV DX,LAST_DMA_PAGE 29 MOV AH,AL ; SAVE THE DATA PATTERN 30 OUT DX,AL ; OUTPUT PAGE REGISTER 31 32;----- VERIFY PAGE REGISTER 8F 33 34 SUB AL,AL ; CHANGE DATA PATTERN BEFORE READ 35 IN AL,DX ; GET THE DATA FROM PAGE REGISTER 36 CMP AL,AH 37 JNZ C26 ; GO IF ERROR 38 CMP AH,0CCM 39 JNZ C25 ; GO IF ERROR 40 MOV AL,033H ; SET UP DATA PATTERN OF 33 41 JMP C22 ; DO DATA 33 42C25: 43 CMP AH,0 ; CHECK DONE 44 JZ C27 ; GO IF YES 45 SUB AL,AL ; SET UP FOR DATA PATTERN 00 46 JMP C22 ; DO DATA 0 47 48;----- ERROR HALT 49C26: 50 HLT ; HALT SYSTEM
This means that the BIOS expects the unmapped adress ranges from 0x81-0x8F(only 0x81, 0x82, 0x83, 0x87, 0x89, 0x8A, 0x8B an 0x8F being available and existent on the ISA DMA chip's page registers) to be available and stored for some reason?
Edit: Implementing those dummy registers makes the diagnostics code increase to 09(Memory Refresh).
Edit: After implementing toggling bit 4 on every DRAM Refresh, it now increases to 0C(In the middle of the 8042 self test)?
This means that the BIOS expects the unmapped adress ranges from 0x81-0x8F(only 0x81, 0x82, 0x83, 0x87, 0x89, 0x8A, 0x8B an 0x8F being available and existent on the ISA DMA chip's page registers) to be available and stored for some reason?
Edit: Implementing those dummy registers makes the diagnostics code increase to 09(Memory Refresh).
No they are not unmapped, just not used for anything useful. The LS612 has 4 address lines so it uses the whole address range 0x80-0x8F.
OK. I've added the missing 0x80 port as well(although it's output port is shared with the 0x80 MFG_PORT debug port, this is no problem, since it's an output port(it gives no input to the software, thus no conflicts)). That part passes completely now. It still won't get past checkpoint 0C. Strangely enough, the breakpoint won't start correctly? When the port is written, the debugger starts the next instruction. But the next instruction isn't the same as in the source code?
1 MOV AL,0CH ; <><><><><><><><><><><><> 2 OUT MFG_PORT,AL ; <><> CHECKPOINT OC <><> 3 4 JNZ ERR0 ; GO IF NOT OK 5 6;----- GET THE SWITCH SETTINGS 7 MOV AL,READ_8042_INPUT ; READ INPUT COMMAND 8 MOV SP:OFFSET C8042C ; SET RETURN ADDRESS 9 JMP SHORT C8042 ; ISSUE COMMAND 10E30B: MOV SP,OFFSET OBF_42B ; SET RETURN ADDRESS 11 JMP SHORT OBF_42 ; GO WAIT FOR RESPONSE 12E30C: IN AL,PORT_A ; GET THE SWITCH 13 OUT DMA_PAGE+1,AL ; SAVE TEMPORARY 14 15;----- WRITE BYTE 0 OF 8042 MEMORY 16 17 MOV AL,WRITE_8042_LOC ; WRITE BYTE COMMAND 18 MOV OFFSET C8042B ; SET RETURN ADDRESS 19 JMP SHORT C8042 ; ISSUE THE COMMAND 20TST4_D: JZ TST4_D1 ; CONTINUE IF COMMAND ACCEPTED 21 22 MOV AL,ODH ; <><><><><><><><><><><><> 23 OUT MFG_PORT,AL ; <><> CHECKPOINT 0D <><> 24 HLT 25TST4_D1: 26 MOV AL,5DH ; ENABLE OUTPUT BUFFER FULL INTERRUPT, 27 OUT PORT_A,AL ; DISABLE KEYBOARD, SET SYSTEM FLAG, 28 JMP SHORT E30A ; PC 1 COMPATIBILITY, INHIBIT OVERRIDE 29 30;----- ISSUE THE COMMAND TO THE 8042 31 32C8042: CLI ; NO INTERRUPTS ALLOWED 33 OUT STATUS_PORT,AL ; SEND COMMAND IN AL REGISTER 34 35 SUB CX,CX ; LOOP COUNT 36C42_1: IN AL,STATUS_PORT ; WAIT FOR THE COMMAND ACCEPTED 37 TEST AL,INPT_BUF_FULL 38 LOOPNZ C42_1 39 RET 40 41;----- WAIT FOR 8042 RESPONSE 42 43OBF_42: SUB CX,CX 44 MOV BL,6 ; 200MS/PER LOOP * 6 =1200 MS + 45C42_2: IN AL,STATUS_PORT ; CHECK FOR RESPONSE 46 TEST AL,OUT_BUP_FULL 47 JNZ C42_3 ; GO IF RESPONSE 48 LOOP C42_2 ; TRY AGAIN 49 DEC BL ; DECREMENT LOOP COUNT 50 JNZ C42_2 51C42_3: RET ; RETURN TO CALLER 52 53;------------------------------------------ 54; TEST.11 : 55; BASE 64K READ/WRITE MEMORY TEST : 56; DESCRIPTION : 57; WRITE/READ/VERIFY DATA PATTERNS : 58; AA,55,FF,01, AND 00 TO 1 ST 64K : 59; OF STORAGE, VERIFY STORAGE : 60; ADDRESSABILITY. ;
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61;------------------------------------------ 62 63;----- FILL MEMORY WITH DATA 64 65E30A: MOV AL,0EH ; <><><><><><><><><><><><> 66 OUT MFG_PORT,AL ; <><> CHECKPOINT 0E <><>
UniPCemu debugger log when testing from the point the value is set to 0Ch:
Debugger log from the point the 0Ch value is written to MFG_PORT(which is the very first instruction in the log).
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I've implemented a bit more of the protected mode segments in real mode, so that stuff like unreal mode will work. Any load to any segment in real mode causes the segment descriptor's base fields to be updated with a new base, while it's high 12 bits are cleared(conforming to 8086-mode 20-bits base addresses).
The 8086 module is already copied to the 80386 module, with the 80386 code adjusted for 32-bits operand size and the timings.c tables for the 80386 implemented as a copy of the 8086 timings, but with 16-bit instructions adjusted to 32-bits(3rd byte of each enter becomes 2(32-bits data modr/m) instead of 1(16-bits data modr/m). I still need to fix the final parameter(immediate word) to specify immediate doubleword. The same applies to the instruction for JMP immediate seg:offs that's reimplemented. Also, the loop* instructions still need proper 32-bit versions.
I've tried booting the Generic Super PC/Turbo XT BIOS on the 80286, but it keeps clearing memory using STOSW infinitely? Does this mean there's a problem with the segment descriptor implementation in real mode? I don't see any protections being fired(#GP, #NP or #SS)? Anyone can see what's going wrong? Can IBM PC XT bioses even run on a IBM PC AT?
Edit: I've just found out by examining the source code of the 286 AT BIOS, that I was working with the 06/10/85 BIOS source code(from intel-assembler) and the first revision of the BIOS(01/10/84) BIOS. I've redownloaded the correct BIOS from minuszerodegrees to verify the correct BIOS...
Edit: It now gets to the diagnostic point 0C again. After looking at the disassembly by the emulator and the disassembly by the original source code by IBM, I notice something odd:
The DMA page register test I'm using for setting a breakpoint in the BIOS is being overwritten with incorrect values during the DMA Page Registe test (Test 08):
1;------------------------------------------ 2; TEST.08 : 3; DMA PAGE REGISTER TEST : 4; DESCRIPTION : 5; WRITE/READ ALL PAGE REGISTERS : 6;------------------------------------------ 7 8;----- CHECKPOINT 08 9 MOV AL,08H ; <><><><><><><><><><><><> 10 OUT MFG_PORT,AL ; <><> CHECKPOINT 08 <><> 11 SUB AL,AL 12 MOV DX,DMA_ PAGE 13 MOV CX,0FFA ; DO ALL DATA PATTERNS 14C22A: OUT DX,AL 15 INC DX 16 INC AL 17 CMP DX,8FH ; TEST DMA PAGES 81 THROUGH 8EH 18 JNZ C22A 19 XCHG AH,AL ; SAVE CURRENT DATA PATTERN 20 DEC AH ; CHECK LAST WRITTEN 21 DEC DX 22C22B: SUB AL,AL ; CHANGE DATA BEFORE READ 23 IN AL,DX 24 CMP AL,AH ; DATA AS WRITTEN? 25 JNZ C26 ; GO ERROR HALT IF NOT 26 DEC AH 27 DEC DX 28 CMP DX,MFG_PORT ; CONTINUE TILL PORT 80 29 JNZ C22B 30 INC AH ; NEXT PATTERN TO RIPPLE 31 MOV AL,AH 32 LOOP C22A
When it reaches the final INC AH in the C22B block, register DX equals the MFG_PORT constant (0x80). Thus the first port rippled with every next pattern(except the first pattern) is port 80h(the diagnostics port, which also sets a breakpoint when set using the Settings menu, in this case 0x0C). Thus the debugger starts when the value 0x0C is written to port 80h. But this isn't the correct value: it's one of the loops at the end of C22B putting a DMA Page register test pattern in the Diagnostics port instead of a DMA Page register?
This problem happens for all loops executed, only the first loop(starting point at checkpoint 08 comment) starts with the correct DMA Page Register port?
Edit: It seems I was right, it DOES log it's rippled test data to the Diagnostics Port. But it does end up at 0C afterward(like I thought):
100:00:19:18.02834: POST Code: 01 200:00:19:18.03530: POST Code: 02 300:00:19:53.05798: POST Code: 03 400:00:19:53.06102: POST Code: 04 500:00:19:53.06192: POST Code: 05 600:00:19:53.06280: POST Code: 06 700:00:19:53.07336: POST Code: 07 800:00:19:53.08588: POST Code: 08 900:00:19:53.09036: POST Code: 00 1000:00:19:53.09524: POST Code: 01 1100:00:19:53.09972: POST Code: 02 1200:00:19:54.00454: POST Code: 03 1300:00:19:54.01054: POST Code: 04 1400:00:19:54.01522: POST Code: 05 1500:00:19:54.01996: POST Code: 06 1600:00:19:54.02572: POST Code: 07 1700:00:19:54.03136: POST Code: 08 1800:00:19:54.03708: POST Code: 09 1900:00:19:54.04268: POST Code: 0A 2000:00:19:54.04916: POST Code: 0B 2100:00:19:54.05536: POST Code: 0C 2200:00:19:54.06052: POST Code: 0D 2300:00:19:54.06560: POST Code: 0E 2400:00:19:54.07076: POST Code: 0F 2500:00:19:54.07584: POST Code: 10 2600:00:19:54.08062: POST Code: 11 2700:00:19:54.08528: POST Code: 12 2800:00:19:54.08998: POST Code: 13 2900:00:19:54.09488: POST Code: 14 3000:00:19:54.09958: POST Code: 15 3100:00:19:55.00462: POST Code: 16 3200:00:19:55.00912: POST Code: 17 3300:00:19:55.01404: POST Code: 18 3400:00:19:55.01852: POST Code: 19 3500:00:19:55.02322: POST Code: 1A 3600:00:19:55.02770: POST Code: 1B 3700:00:19:55.03262: POST Code: 1C 3800:00:19:55.03710: POST Code: 1D 3900:00:19:55.04158: POST Code: 1E 4000:00:19:55.04648: POST Code: 1F 4100:00:19:55.05096: POST Code: 20 4200:00:19:55.05566: POST Code: 21 4300:00:19:55.06054: POST Code: 22 4400:00:19:55.06788: POST Code: 23 4500:00:19:55.07260: POST Code: 24 4600:00:19:55.07794: POST Code: 25 4700:00:19:56.03544: POST Code: 26 4800:00:19:56.04038: POST Code: 27 4900:00:19:56.04514: POST Code: 28 5000:00:19:56.04962: POST Code: 29 5100:00:19:56.05456: POST Code: 2A 5200:00:19:56.05902: POST Code: 2B 5300:00:19:56.06372: POST Code: 2C 5400:00:19:56.06858: POST Code: 2D 5500:00:19:56.07330: POST Code: 2E 5600:00:19:56.07798: POST Code: 2F 5700:00:19:56.08298: POST Code: 30 5800:00:19:56.08744: POST Code: 31 5900:00:19:56.09234: POST Code: 32 6000:00:19:56.09680: POST Code: 33
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6100:00:19:57.00146: POST Code: 34 6200:00:19:57.00634: POST Code: 35 6300:00:19:57.01184: POST Code: 36 6400:00:19:57.01730: POST Code: 37 6500:00:19:57.02178: POST Code: 38 6600:00:19:57.02672: POST Code: 39 6700:00:19:57.03116: POST Code: 3A 6800:00:19:57.03660: POST Code: 3B 6900:00:19:57.04150: POST Code: 3C 7000:00:19:57.04598: POST Code: 3D 7100:00:19:57.05042: POST Code: 3E 7200:00:19:57.05530: POST Code: 3F 7300:00:19:57.05976: POST Code: 40 7400:00:19:57.06424: POST Code: 41 7500:00:19:57.06870: POST Code: 42 7600:00:19:57.07364: POST Code: 43 7700:00:19:57.07836: POST Code: 44 7800:00:19:57.08282: POST Code: 45 7900:00:19:57.08728: POST Code: 46 8000:00:19:57.09216: POST Code: 47 8100:00:19:57.09780: POST Code: 48 8200:00:19:58.00254: POST Code: 49 8300:00:19:58.00756: POST Code: 4A 8400:00:19:58.01256: POST Code: 4B 8500:00:19:58.01704: POST Code: 4C 8600:00:19:58.02150: POST Code: 4D 8700:00:19:58.02642: POST Code: 4E 8800:00:19:58.03112: POST Code: 4F 8900:00:19:58.03558: POST Code: 50 9000:00:19:58.04044: POST Code: 51 9100:00:19:58.04494: POST Code: 52 9200:00:19:58.04940: POST Code: 53 9300:00:19:58.05446: POST Code: 54 9400:00:19:58.05892: POST Code: 55 9500:00:19:58.06340: POST Code: 56 9600:00:19:58.06808: POST Code: 57 9700:00:19:58.07292: POST Code: 58 9800:00:19:58.07740: POST Code: 59 9900:00:19:58.08236: POST Code: 5A 10000:00:19:58.08686: POST Code: 5B 10100:00:19:58.09182: POST Code: 5C 10200:00:19:58.09630: POST Code: 5D 10300:00:19:59.00076: POST Code: 5E 10400:00:19:59.04906: POST Code: 5F 10500:00:19:59.05388: POST Code: 60 10600:00:19:59.05854: POST Code: 61 10700:00:19:59.06412: POST Code: 62 10800:00:19:59.06878: POST Code: 63 10900:00:19:59.07358: POST Code: 64 11000:00:19:59.07814: POST Code: 65 11100:00:19:59.08398: POST Code: 66 11200:00:19:59.08854: POST Code: 67 11300:00:19:59.09294: POST Code: 68 11400:00:19:59.09728: POST Code: 69 11500:00:19:60.00230: POST Code: 6A 11600:00:19:60.00710: POST Code: 6B 11700:00:19:60.01178: POST Code: 6C 11800:00:19:60.01666: POST Code: 6D 11900:00:19:60.02168: POST Code: 6E 12000:00:19:60.02604: POST Code: 6F 12100:00:19:60.03068: POST Code: 70 12200:00:19:60.03508: POST Code: 71 12300:00:19:60.04030: POST Code: 72 12400:00:19:60.04640: POST Code: 73 12500:00:19:60.05110: POST Code: 74 12600:00:19:60.05626: POST Code: 75 12700:00:19:60.06068: POST Code: 76 12800:00:19:60.06504: POST Code: 77 12900:00:19:60.07010: POST Code: 78 13000:00:19:60.07490: POST Code: 79 13100:00:19:60.07948: POST Code: 7A 13200:00:19:60.08386: POST Code: 7B 13300:00:19:60.09058: POST Code: 7C 13400:00:19:60.09500: POST Code: 7D 13500:00:19:60.09936: POST Code: 7E 13600:00:19:61.00406: POST Code: 7F 13700:00:19:61.00934: POST Code: 80 13800:00:19:61.01454: POST Code: 81 13900:00:19:61.01910: POST Code: 82 14000:00:19:61.02402: POST Code: 83 14100:00:19:61.02858: POST Code: 84 14200:00:19:61.03414: POST Code: 85 14300:00:19:61.03916: POST Code: 86 14400:00:19:61.04384: POST Code: 87 14500:00:19:61.04842: POST Code: 88 14600:00:19:61.05292: POST Code: 89 14700:00:19:61.05776: POST Code: 8A 14800:00:19:61.06236: POST Code: 8B 14900:00:19:61.06782: POST Code: 8C 15000:00:19:61.07388: POST Code: 8D 15100:00:19:61.07868: POST Code: 8E 15200:00:19:61.08334: POST Code: 8F 15300:00:19:61.08776: POST Code: 90 15400:00:19:61.09352: POST Code: 91 15500:00:19:61.09810: POST Code: 92 15600:00:19:62.00246: POST Code: 93 15700:00:19:62.00764: POST Code: 94 15800:00:19:62.01200: POST Code: 95 15900:00:19:62.01638: POST Code: 96 16000:00:19:62.02126: POST Code: 97 16100:00:19:62.02566: POST Code: 98 16200:00:19:62.03002: POST Code: 99 16300:00:19:62.03492: POST Code: 9A 16400:00:19:62.03942: POST Code: 9B 16500:00:19:62.08686: POST Code: 9C 16600:00:19:62.09126: POST Code: 9D 16700:00:19:62.09630: POST Code: 9E 16800:00:19:63.00096: POST Code: 9F 16900:00:19:63.00656: POST Code: A0 17000:00:19:63.01094: POST Code: A1 17100:00:19:63.01530: POST Code: A2 17200:00:19:63.02042: POST Code: A3 17300:00:19:63.02478: POST Code: A4 17400:00:19:63.02952: POST Code: A5 17500:00:19:63.03392: POST Code: A6 17600:00:19:63.03872: POST Code: A7 17700:00:19:63.04404: POST Code: A8 17800:00:19:63.04946: POST Code: A9 17900:00:19:63.05384: POST Code: AA 18000:00:19:63.05868: POST Code: AB 18100:00:19:63.06326: POST Code: AC 18200:00:19:63.06812: POST Code: AD 18300:00:19:63.07314: POST Code: AE 18400:00:19:63.07864: POST Code: AF 18500:00:19:63.08464: POST Code: B0 18600:00:19:63.08980: POST Code: B1 18700:00:19:63.09418: POST Code: B2 18800:00:19:63.09908: POST Code: B3 18900:00:19:64.00440: POST Code: B4 19000:00:19:64.00992: POST Code: B5 19100:00:19:64.01508: POST Code: B6 19200:00:19:64.01948: POST Code: B7 19300:00:19:64.02466: POST Code: B8 19400:00:19:64.03052: POST Code: B9 19500:00:19:64.03490: POST Code: BA 19600:00:19:64.04024: POST Code: BB 19700:00:19:64.04558: POST Code: BC 19800:00:19:64.05008: POST Code: BD 19900:00:19:64.05502: POST Code: BE 20000:00:19:64.05950: POST Code: BF 20100:00:19:64.06420: POST Code: C0 20200:00:19:64.06940: POST Code: C1 20300:00:19:64.07458: POST Code: C2 20400:00:19:64.08038: POST Code: C3 20500:00:19:64.08488: POST Code: C4 20600:00:19:64.08990: POST Code: C5 20700:00:19:64.09478: POST Code: C6 20800:00:19:65.00012: POST Code: C7 20900:00:19:65.00566: POST Code: C8 21000:00:19:65.01014: POST Code: C9 21100:00:19:65.01464: POST Code: CA 21200:00:19:65.01958: POST Code: CB 21300:00:19:65.02410: POST Code: CC 21400:00:19:65.02856: POST Code: CD 21500:00:19:65.03326: POST Code: CE 21600:00:19:65.03782: POST Code: CF 21700:00:19:65.04230: POST Code: D0 21800:00:19:65.04676: POST Code: D1 21900:00:19:65.05180: POST Code: D2 22000:00:19:65.05636: POST Code: D3 22100:00:19:65.06086: POST Code: D4 22200:00:19:65.06590: POST Code: D5 22300:00:19:65.07036: POST Code: D6 22400:00:19:65.07496: POST Code: D7 22500:00:19:65.07992: POST Code: D8 22600:00:19:66.02558: POST Code: D9 22700:00:19:66.03006: POST Code: DA 22800:00:19:66.03458: POST Code: DB 22900:00:19:66.03964: POST Code: DC 23000:00:19:66.04422: POST Code: DD 23100:00:19:66.04882: POST Code: DE 23200:00:19:66.05320: POST Code: DF 23300:00:19:66.05756: POST Code: E0 23400:00:19:66.06264: POST Code: E1 23500:00:19:66.06700: POST Code: E2 23600:00:19:66.07202: POST Code: E3 23700:00:19:66.07640: POST Code: E4 23800:00:19:66.08148: POST Code: E5 23900:00:19:66.08586: POST Code: E6 24000:00:19:66.09450: POST Code: E7 24100:00:19:67.00152: POST Code: E8 24200:00:19:67.00684: POST Code: E9 24300:00:19:67.01122: POST Code: EA 24400:00:19:67.01724: POST Code: EB 24500:00:19:67.02162: POST Code: EC 24600:00:19:67.02622: POST Code: ED 24700:00:19:67.03120: POST Code: EE 24800:00:19:67.03560: POST Code: EF 24900:00:19:67.04010: POST Code: F0 25000:00:19:67.04456: POST Code: F1 25100:00:19:67.04944: POST Code: F2 25200:00:19:67.05394: POST Code: F3 25300:00:19:67.05840: POST Code: F4 25400:00:19:67.06304: POST Code: F5 25500:00:19:67.06784: POST Code: F6 25600:00:19:67.07232: POST Code: F7 25700:00:19:67.07680: POST Code: F8 25800:00:19:67.08188: POST Code: F9 25900:00:19:67.08740: POST Code: FA 26000:00:19:67.09186: POST Code: FB 26100:00:19:67.09698: POST Code: FC 26200:00:19:68.00172: POST Code: FD 26300:00:19:68.00708: POST Code: 09 26400:00:19:68.05416: POST Code: 0A 26500:00:19:68.05446: POST Code: 0B 26600:00:24:58.09034: POST Code: 0C
That log was made using the new debugger log setting to log POST codes written to 80h(only when it changes it's value).
The good news is that it DOES end up at the point I want it to be. But it does wrong anyway, for some reason. I'll need to implement a skip value for debugging point 0B at the end here.
Edit: I've implemented a skip value. It gets to point 0C, then it executes a JNZ jump to a HLT instruction, because the 8042 emulation is apparently bad. So the 8042 emulation does have an error?
The IRQ8042 function is called by the PS/2 keyboard and mouse when they have anything for the 8042 to receive, as well as when the 8042 PS/2 port is selected using function A8. This loads any new values into the 8042 chip's output buffer(8042 perspective) and raises any IRQs when enabled.
This is the output I currently get:
100:00:14:02.08082: POST Code: 01 200:00:14:02.08861: POST Code: 02 300:00:14:37.01219: POST Code: 03 400:00:14:37.01495: POST Code: 04 500:00:14:37.01599: POST Code: 05 600:00:14:37.01687: POST Code: 06 700:00:14:37.02898: POST Code: 07 800:00:14:37.04017: POST Code: 08 900:00:14:37.04502: POST Code: 00 1000:00:14:37.04965: POST Code: 01 1100:00:14:37.05431: POST Code: 02 1200:00:14:37.05920: POST Code: 03 1300:00:14:37.06423: POST Code: 04 1400:00:14:37.06867: POST Code: 05 1500:00:14:37.07349: POST Code: 06 1600:00:14:37.07796: POST Code: 07 1700:00:14:37.08261: POST Code: 08 1800:00:14:37.08715: POST Code: 09 1900:00:14:37.09224: POST Code: 0A 2000:00:14:37.09696: POST Code: 0B 2100:00:14:38.00139: POST Code: 0C 2200:00:14:38.00611: POST Code: 0D 2300:00:14:38.01079: POST Code: 0E 2400:00:14:38.01521: POST Code: 0F 2500:00:14:38.01984: POST Code: 10 2600:00:14:38.02522: POST Code: 11 2700:00:14:38.07377: POST Code: 12 2800:00:14:38.07824: POST Code: 13 2900:00:14:38.08429: POST Code: 14 3000:00:14:38.08918: POST Code: 15 3100:00:14:38.09365: POST Code: 16 3200:00:14:38.09808: POST Code: 17 3300:00:14:39.00292: POST Code: 18 3400:00:14:39.00734: POST Code: 19 3500:00:14:39.01179: POST Code: 1A 3600:00:14:39.01669: POST Code: 1B 3700:00:14:39.02152: POST Code: 1C 3800:00:14:39.02607: POST Code: 1D 3900:00:14:39.03070: POST Code: 1E 4000:00:14:39.03586: POST Code: 1F 4100:00:14:39.04076: POST Code: 20 4200:00:14:39.04557: POST Code: 21 4300:00:14:39.05124: POST Code: 22 4400:00:14:39.05584: POST Code: 23 4500:00:14:39.06184: POST Code: 24 4600:00:14:39.06627: POST Code: 25 4700:00:14:39.07067: POST Code: 26 4800:00:14:39.07514: POST Code: 27 4900:00:14:39.08007: POST Code: 28 5000:00:14:39.08453: POST Code: 29 5100:00:14:39.08980: POST Code: 2A 5200:00:14:39.09471: POST Code: 2B 5300:00:14:39.09914: POST Code: 2C 5400:00:14:40.00384: POST Code: 2D 5500:00:14:40.00876: POST Code: 2E 5600:00:14:40.01331: POST Code: 2F 5700:00:14:40.01776: POST Code: 30 5800:00:14:40.02611: POST Code: 31 5900:00:14:40.03054: POST Code: 32 6000:00:14:40.03498: POST Code: 33
…Show last 211 lines
6100:00:14:40.04001: POST Code: 34 6200:00:14:40.04471: POST Code: 35 6300:00:14:40.04915: POST Code: 36 6400:00:14:40.05428: POST Code: 37 6500:00:14:40.05872: POST Code: 38 6600:00:14:40.06341: POST Code: 39 6700:00:14:40.06834: POST Code: 3A 6800:00:14:40.07276: POST Code: 3B 6900:00:14:40.07721: POST Code: 3C 7000:00:14:40.08212: POST Code: 3D 7100:00:14:40.08657: POST Code: 3E 7200:00:14:40.09097: POST Code: 3F 7300:00:14:40.09540: POST Code: 40 7400:00:14:41.00042: POST Code: 41 7500:00:14:41.00485: POST Code: 42 7600:00:14:41.00930: POST Code: 43 7700:00:14:41.01371: POST Code: 44 7800:00:14:41.01877: POST Code: 45 7900:00:14:41.02319: POST Code: 46 8000:00:14:41.02763: POST Code: 47 8100:00:14:41.03292: POST Code: 48 8200:00:14:41.03768: POST Code: 49 8300:00:14:41.04210: POST Code: 4A 8400:00:14:41.04707: POST Code: 4B 8500:00:14:41.05149: POST Code: 4C 8600:00:14:42.00028: POST Code: 4D 8700:00:14:42.00482: POST Code: 4E 8800:00:14:42.00936: POST Code: 4F 8900:00:14:42.01455: POST Code: 50 9000:00:14:42.01949: POST Code: 51 9100:00:14:42.02423: POST Code: 52 9200:00:14:42.02856: POST Code: 53 9300:00:14:42.03413: POST Code: 54 9400:00:14:42.03861: POST Code: 55 9500:00:14:42.04295: POST Code: 56 9600:00:14:42.04843: POST Code: 57 9700:00:14:42.05340: POST Code: 58 9800:00:14:42.05785: POST Code: 59 9900:00:14:42.06292: POST Code: 5A 10000:00:14:42.06750: POST Code: 5B 10100:00:14:42.07185: POST Code: 5C 10200:00:14:42.07685: POST Code: 5D 10300:00:14:42.08119: POST Code: 5E 10400:00:14:42.08576: POST Code: 5F 10500:00:14:42.09020: POST Code: 60 10600:00:14:42.09464: POST Code: 61 10700:00:14:42.09943: POST Code: 62 10800:00:14:43.00387: POST Code: 63 10900:00:14:43.00833: POST Code: 64 11000:00:14:43.01341: POST Code: 65 11100:00:14:43.01783: POST Code: 66 11200:00:14:43.02227: POST Code: 67 11300:00:14:43.02731: POST Code: 68 11400:00:14:43.03175: POST Code: 69 11500:00:14:43.03618: POST Code: 6A 11600:00:14:43.04060: POST Code: 6B 11700:00:14:43.04559: POST Code: 6C 11800:00:14:43.05030: POST Code: 6D 11900:00:14:43.05509: POST Code: 6E 12000:00:14:43.06046: POST Code: 6F 12100:00:14:43.06553: POST Code: 70 12200:00:14:43.07017: POST Code: 71 12300:00:14:43.07585: POST Code: 72 12400:00:14:43.08096: POST Code: 73 12500:00:14:43.08546: POST Code: 74 12600:00:14:43.08979: POST Code: 75 12700:00:14:43.09564: POST Code: 76 12800:00:14:44.00007: POST Code: 77 12900:00:14:44.00479: POST Code: 78 13000:00:14:44.01014: POST Code: 79 13100:00:14:44.01509: POST Code: 7A 13200:00:14:44.02106: POST Code: 7B 13300:00:14:44.02604: POST Code: 7C 13400:00:14:44.03035: POST Code: 7D 13500:00:14:44.03736: POST Code: 7E 13600:00:14:44.04167: POST Code: 7F 13700:00:14:44.04624: POST Code: 80 13800:00:14:44.05068: POST Code: 81 13900:00:14:44.05501: POST Code: 82 14000:00:14:44.06004: POST Code: 83 14100:00:14:44.06482: POST Code: 84 14200:00:14:44.06926: POST Code: 85 14300:00:14:44.07423: POST Code: 86 14400:00:14:44.07879: POST Code: 87 14500:00:14:44.08312: POST Code: 88 14600:00:14:44.08794: POST Code: 89 14700:00:14:44.09236: POST Code: 8A 14800:00:14:45.04209: POST Code: 8B 14900:00:14:45.04653: POST Code: 8C 15000:00:14:45.05102: POST Code: 8D 15100:00:14:45.05545: POST Code: 8E 15200:00:14:45.06034: POST Code: 8F 15300:00:14:45.06540: POST Code: 90 15400:00:14:45.06984: POST Code: 91 15500:00:14:45.07479: POST Code: 92 15600:00:14:45.08015: POST Code: 93 15700:00:14:45.08480: POST Code: 94 15800:00:14:45.09009: POST Code: 95 15900:00:14:45.09575: POST Code: 96 16000:00:14:46.00023: POST Code: 97 16100:00:14:46.00465: POST Code: 98 16200:00:14:46.00944: POST Code: 99 16300:00:14:46.01386: POST Code: 9A 16400:00:14:46.01850: POST Code: 9B 16500:00:14:46.02331: POST Code: 9C 16600:00:14:46.02775: POST Code: 9D 16700:00:14:46.03220: POST Code: 9E 16800:00:14:46.03714: POST Code: 9F 16900:00:14:46.04160: POST Code: A0 17000:00:14:46.04629: POST Code: A1 17100:00:14:46.05073: POST Code: A2 17200:00:14:46.05514: POST Code: A3 17300:00:14:46.05987: POST Code: A4 17400:00:14:46.06429: POST Code: A5 17500:00:14:46.06903: POST Code: A6 17600:00:14:46.07348: POST Code: A7 17700:00:14:46.07844: POST Code: A8 17800:00:14:46.08344: POST Code: A9 17900:00:14:46.08840: POST Code: AA 18000:00:14:46.09343: POST Code: AB 18100:00:14:46.09775: POST Code: AC 18200:00:14:47.00228: POST Code: AD 18300:00:14:47.00661: POST Code: AE 18400:00:14:47.01128: POST Code: AF 18500:00:14:47.01723: POST Code: B0 18600:00:14:47.02179: POST Code: B1 18700:00:14:47.02659: POST Code: B2 18800:00:14:47.03114: POST Code: B3 18900:00:14:47.03612: POST Code: B4 19000:00:14:47.04042: POST Code: B5 19100:00:14:47.04478: POST Code: B6 19200:00:14:47.04984: POST Code: B7 19300:00:14:47.05516: POST Code: B8 19400:00:14:47.05949: POST Code: B9 19500:00:14:47.06448: POST Code: BA 19600:00:14:47.06881: POST Code: BB 19700:00:14:47.07339: POST Code: BC 19800:00:14:47.07783: POST Code: BD 19900:00:14:47.08371: POST Code: BE 20000:00:14:47.08859: POST Code: BF 20100:00:14:47.09317: POST Code: C0 20200:00:14:47.09792: POST Code: C1 20300:00:14:48.00226: POST Code: C2 20400:00:14:48.00689: POST Code: C3 20500:00:14:48.01183: POST Code: C4 20600:00:14:48.01627: POST Code: C5 20700:00:14:48.02190: POST Code: C6 20800:00:14:48.07122: POST Code: C7 20900:00:14:48.07590: POST Code: C8 21000:00:14:48.08029: POST Code: C9 21100:00:14:48.08581: POST Code: CA 21200:00:14:48.09065: POST Code: CB 21300:00:14:48.09505: POST Code: CC 21400:00:14:48.09982: POST Code: CD 21500:00:14:49.00475: POST Code: CE 21600:00:14:49.00919: POST Code: CF 21700:00:14:49.01483: POST Code: D0 21800:00:14:49.02105: POST Code: D1 21900:00:14:49.02546: POST Code: D2 22000:00:14:49.02991: POST Code: D3 22100:00:14:49.03441: POST Code: D4 22200:00:14:49.03905: POST Code: D5 22300:00:14:49.04347: POST Code: D6 22400:00:14:49.04788: POST Code: D7 22500:00:14:49.05254: POST Code: D8 22600:00:14:49.05696: POST Code: D9 22700:00:14:49.06139: POST Code: DA 22800:00:14:49.06584: POST Code: DB 22900:00:14:49.07039: POST Code: DC 23000:00:14:49.07529: POST Code: DD 23100:00:14:49.07973: POST Code: DE 23200:00:14:49.08423: POST Code: DF 23300:00:14:49.08856: POST Code: E0 23400:00:14:49.09381: POST Code: E1 23500:00:14:49.09836: POST Code: E2 23600:00:14:50.00268: POST Code: E3 23700:00:14:50.00772: POST Code: E4 23800:00:14:50.01216: POST Code: E5 23900:00:14:50.01670: POST Code: E6 24000:00:14:50.02183: POST Code: E7 24100:00:14:50.02615: POST Code: E8 24200:00:14:50.03053: POST Code: E9 24300:00:14:50.03530: POST Code: EA 24400:00:14:50.04047: POST Code: EB 24500:00:14:50.04479: POST Code: EC 24600:00:14:50.04934: POST Code: ED 24700:00:14:50.05441: POST Code: EE 24800:00:14:50.05895: POST Code: EF 24900:00:14:50.06472: POST Code: F0 25000:00:14:50.07065: POST Code: F1 25100:00:14:50.07507: POST Code: F2 25200:00:14:50.07961: POST Code: F3 25300:00:14:50.08487: POST Code: F4 25400:00:14:50.08995: POST Code: F5 25500:00:14:50.09429: POST Code: F6 25600:00:14:50.09936: POST Code: F7 25700:00:14:51.00414: POST Code: F8 25800:00:14:51.00899: POST Code: F9 25900:00:14:51.01399: POST Code: FA 26000:00:14:51.01915: POST Code: FB 26100:00:14:51.02408: POST Code: FC 26200:00:14:51.02999: POST Code: FD 26300:00:14:51.03625: POST Code: 09 26400:00:14:52.02716: POST Code: 0A 26500:00:14:52.02747: POST Code: 0B 26600:00:14:52.02810: POST Code: 0C 26700:00:14:52.02902: POST Code: 0E 26800:00:14:52.02937: POST Code: 0F 26900:00:16:19.01612: POST Code: 32 27000:00:16:57.06425: POST Code: 11
So I can conclude it errors our somewhere in the STGTST_CNT function? I've tested it until the first LODSW loop, which reads 0xAA55 values from memory.
I just though about something: The 80286 and 80386 raise their high (above 1MB) address lines on reset for code segment accesses, until CS is loaded through a intersegment CALL or JMP instruction. So when it resets it reads the BIOS code from selector OR 0xF00000(OR 0xFFF00000 on a 80386 CPU). Then when the CS register is loaded, the bios clears those automatic assertions, instead using the lower 1MB area to address the ROM(as long as it's using segment 0xF000) instead.
So before resetting those lines (at CPU reset), the BIOS must be at physical address 0xFF0000(segment F000)-0xFFFFFF for a 64k BIOS ROM. But after CS is loaded, it's supposed to be at 0xF0000-0xFFFFF.
Does the ROM decode both the high addresses and the low addresses at the same time? So it responds to both ranges(since it doesn't know anything about the CS being loaded after reset or not)?
Edit: After implementing proper segment and address lines, it ends up with POST Diagnostic code 11h, which, according to http://www.postcodemaster.com/IBMAT.shtml is:
11 - Verify 286 LGDT/SGDT and LIDT/SIDT Instructions
So there's an error with my 80286+ L/S GDT/IDT instructions?
Edit: This doesn't seem to be the case. At 11h it's actually verifying the DRAM Refresh rate to be within expected limits:
1 MOV AL,11H ; <><><><><><><><><><><><> 2 OUT MFG_PORT,AL ; <><> CHECKPOINT 11 <><> 3 4;----- VERIFY SPEED/REFRESH CLOCK RATES ( ERROR = 1 LONG AND 1 SHORT BEEP ) 5 XOR BL,BL ; CLEAR REFRESH CYCLE REPEAT COUNT 6 XOR CX,CX ; INITIALIZE SPEED RATE REGISTER 7 EVEN ; PLACE ON EVEN WORD BOUNDARY 8C34: 9 IN AL,PORT_B ; READ REFRESH BIT REGISTER 10 TEST AL,REFRFSH_BIT ; MASK FOR BIT 11 LOOPZ C34 ; DECREMENT LOOP COUNTER TILL ON 12C35: ; superfury: address 05AE 13 IN AL,PORT_B ; READ REFRESH BIT REGISTER 14 TEST AL,REFRFESH_BIT ; MASK FOR BIT 15 LOOPNZ C35 ; DECREMENT LOOP COUNTER TILL OFF 16 ; superfury: addr 5B4 17 DEC BL ; DECREMENT REFRESH CYCLE REPEAT COUNT 18 JNZ C34 ; REPEAT TILL CYCLE COUNT DONE 19 ; addr 5B8; CX=6761 20 CMP CX,RATE_UPPER ; CHECK FOR RATE BELOW UPPER LIMIT 21 JAE C36 ; SKIP ERROR BEEP IF BELOW MAXIMUM 22C36E: 23 MOV DX,0101H ; GET BEEP COUNTS FOR REFRESH ERROR 24 CALL ERR_BEEP ; CALL TO POST ERROR BEEP ROUTINES 25 HLT ; HALT SYSTEM - BAD REFRESH RATE 26C36I 27 CMP CX,RATE_LOWER ; CHECK FOR RATE ABOVE LOWER LIMIT 28 JA C36E ; GO TO ERROR BEEP IF BELOW MINIMUM 29 30;----- GET THE INPUT BUFFER (SWITCH SETTINGS) 31 IN AL,DMA_PAGE+1 ; GET THE SWITCH SETTINGS 32 AND AL,KEY_BD_INHIB+DSP_JMP+MFG_LOOP+BASE_MEM+BASE_MEM8 ; STRIP BITS 33 MOV @MFG_TST,AL ; SAVE SETTINDS 34 SUB AL,AL ; RESET DMA_PAGE 35 OUT DMA_PAGE+1,AL
My emulation gets 0x6761 in CX when it reaches the rate check compares. It needs to be within 0xF8A7-0xF9F0 range for the BIOS to verify correct speed. So my emulator's DMA refresh speed is either too slow, or the bit isn't toggling fast enough?
Edit: I've modified the DMA transfers to take 10 14MHz cycles instead of 9 and moved the toggling of the DRAM Refresh bit to the DRAM DREQ check of the DMA controller channel 0 handler. Now the entire check passes.
It now crashes on the SIDT/LIDT/SGDT/LGDT instruction check.
Edit: Managed to fix the instructions. It now gets to the point it loads 1 into AX and executes a LMSW AX instruction to switch to protected mode. Yay! 😀
Then it executes a long intersegment jump to flush it's descriptor cache, at which point it triple faults(I see this because I end up at F000:FFFF again, after which all CPU checks start again). So there's a problem with loading that CS segment descriptor now, it seems.
Looking at the access rights in the CS descriptor, it's byte contains 0x93. which means writable data segment, not accessed, not Expanding down?
Looking at the BIOS again, it's trying to jump to 0040:1D73 for some reason? That cannot be correct? Segment descriptor 40h points to the start of the BIOS ROM?
Edit: It was reading the descriptor wrong. It saw a TSS descriptor instead of a Code/Data segment(S bit needs to be cleared for it to be a TSS). It now correctly goes and load the Code Segment(CS). After that, it tries to execute a RET, which results in a triple fault, resetting the CPU.
Edit: Managed by fixing the Descriptor Privilege Check done on the SS (and other) descriptor's DPL comparing to CPL and RPL(instead of comparing to CPL and segment index). Now that part of the BIOS works without much problems.
23 - Advanced Video Card Initialization Failure or Invalid Switch Setting
The current diagnostic log:
100:00:03:19.00991: POST Code: 01 200:00:03:19.01499: POST Code: 02 300:00:03:44.06131: POST Code: 03 400:00:03:44.06352: POST Code: 04 500:00:03:44.06434: POST Code: 05 600:00:03:44.06495: POST Code: 06 700:00:03:44.07352: POST Code: 07 800:00:03:44.08183: POST Code: 08 900:00:03:44.08671: POST Code: 00 1000:00:03:44.08961: POST Code: 01 1100:00:03:44.09273: POST Code: 02 1200:00:03:44.09562: POST Code: 03 1300:00:03:44.09930: POST Code: 04 1400:00:03:45.00219: POST Code: 05 1500:00:03:45.00540: POST Code: 06 1600:00:03:45.00828: POST Code: 07 1700:00:03:45.01119: POST Code: 08 1800:00:03:45.01480: POST Code: 09 1900:00:03:45.01767: POST Code: 0A 2000:00:03:45.02057: POST Code: 0B 2100:00:03:45.02344: POST Code: 0C 2200:00:03:45.02632: POST Code: 0D 2300:00:03:45.03019: POST Code: 0E 2400:00:03:45.03310: POST Code: 0F 2500:00:03:45.03598: POST Code: 10 2600:00:03:45.03885: POST Code: 11 2700:00:03:45.04174: POST Code: 12 2800:00:03:45.04539: POST Code: 13 2900:00:03:45.04848: POST Code: 14 3000:00:03:45.05137: POST Code: 15 3100:00:03:45.05445: POST Code: 16 3200:00:03:45.05735: POST Code: 17 3300:00:03:45.06021: POST Code: 18 3400:00:03:45.06487: POST Code: 19 3500:00:03:45.06864: POST Code: 1A 3600:00:03:45.07194: POST Code: 1B 3700:00:03:45.07483: POST Code: 1C 3800:00:03:45.07770: POST Code: 1D 3900:00:03:45.08101: POST Code: 1E 4000:00:03:45.08464: POST Code: 1F 4100:00:03:45.08752: POST Code: 20 4200:00:03:45.09040: POST Code: 21 4300:00:03:45.09338: POST Code: 22 4400:00:03:45.09627: POST Code: 23 4500:00:03:45.09996: POST Code: 24 4600:00:03:46.00286: POST Code: 25 4700:00:03:46.00574: POST Code: 26 4800:00:03:46.00861: POST Code: 27 4900:00:03:46.01153: POST Code: 28 5000:00:03:46.01534: POST Code: 29 5100:00:03:46.01823: POST Code: 2A 5200:00:03:46.02110: POST Code: 2B 5300:00:03:46.02400: POST Code: 2C 5400:00:03:46.02689: POST Code: 2D 5500:00:03:46.03037: POST Code: 2E 5600:00:03:46.03327: POST Code: 2F 5700:00:03:46.03613: POST Code: 30 5800:00:03:46.03923: POST Code: 31 5900:00:03:46.04244: POST Code: 32 6000:00:03:46.04562: POST Code: 33
…Show last 227 lines
6100:00:03:46.04935: POST Code: 34 6200:00:03:46.05266: POST Code: 35 6300:00:03:46.05553: POST Code: 36 6400:00:03:46.05862: POST Code: 37 6500:00:03:46.06149: POST Code: 38 6600:00:03:46.06502: POST Code: 39 6700:00:03:46.06819: POST Code: 3A 6800:00:03:46.07150: POST Code: 3B 6900:00:03:46.07460: POST Code: 3C 7000:00:03:46.07768: POST Code: 3D 7100:00:03:46.08118: POST Code: 3E 7200:00:03:46.08509: POST Code: 3F 7300:00:03:46.08852: POST Code: 40 7400:00:03:46.09161: POST Code: 41 7500:00:03:46.09621: POST Code: 42 7600:00:03:47.00011: POST Code: 43 7700:00:03:47.06066: POST Code: 44 7800:00:03:47.06371: POST Code: 45 7900:00:03:47.06668: POST Code: 46 8000:00:03:47.06971: POST Code: 47 8100:00:03:47.07353: POST Code: 48 8200:00:03:47.07679: POST Code: 49 8300:00:03:47.07979: POST Code: 4A 8400:00:03:47.08274: POST Code: 4B 8500:00:03:47.08582: POST Code: 4C 8600:00:03:47.08926: POST Code: 4D 8700:00:03:47.09223: POST Code: 4E 8800:00:03:47.09518: POST Code: 4F 8900:00:03:47.09812: POST Code: 50 9000:00:03:48.00108: POST Code: 51 9100:00:03:48.00430: POST Code: 52 9200:00:03:48.00726: POST Code: 53 9300:00:03:48.01024: POST Code: 54 9400:00:03:48.01337: POST Code: 55 9500:00:03:48.01632: POST Code: 56 9600:00:03:48.01973: POST Code: 57 9700:00:03:48.02270: POST Code: 58 9800:00:03:48.02564: POST Code: 59 9900:00:03:48.02868: POST Code: 5A 10000:00:03:48.03166: POST Code: 5B 10100:00:03:48.03508: POST Code: 5C 10200:00:03:48.03804: POST Code: 5D 10300:00:03:48.04100: POST Code: 5E 10400:00:03:48.04395: POST Code: 5F 10500:00:03:48.04690: POST Code: 60 10600:00:03:48.04983: POST Code: 61 10700:00:03:48.05326: POST Code: 62 10800:00:03:48.05619: POST Code: 63 10900:00:03:48.05914: POST Code: 64 11000:00:03:48.06211: POST Code: 65 11100:00:03:48.06528: POST Code: 66 11200:00:03:48.06878: POST Code: 67 11300:00:03:48.07173: POST Code: 68 11400:00:03:48.07468: POST Code: 69 11500:00:03:48.07763: POST Code: 6A 11600:00:03:48.08058: POST Code: 6B 11700:00:03:48.08353: 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So protected mode works:) Now only need to fix the issues left.
I've managed to get it as far as to start testing the 1MB+ extended memory. But immediately when the first block of extended memory is checked using REP STOSW:
1HOW_BIG_2A: 2 SUB AX,AX ; WRITE ZEROS 3 MOV CX,2000H*4 ; SET COUNT FOR 32K WORDS 4 REP STOSW ; FILL 32K WORDS
Now the ES descriptor loaded earlier is cleared in the GDT(the GDT entry is cleared by the operation)?
Edit: Examining the memory dump from the start of the test (when the procedure is called) reveals that the IDT entry is already cleared beforehand. Thus the descriptor is read correctly. So that means that the previous BIOS check does overwrite the GDT, but doesn't restore it(fully)?
Edit: Looking at the disassembly just before the function, at the first REP STOSW, I see that the processor is supposed to address 1M+, but the A20 line is still disabled? So the address wraps back to 0, thus clearing the first 64K of RAM, which also contains the GDT. Then, it starts to reload the DS entry, based on a PUSH ES; PUSH ES; POP DS instruction, where pushing ES to the stack, then POPping DS back from the stack reloads the DS descriptor from the GDT, which is erased by the REP STOSW, because it wraps around 1M until 2M. So (with the current 6MB RAM) it will clear the main GDT every 2MB, so at 1M-1M+64K, 3M-3M+64k and 5M-5M+64k. Although the first loading of the GDT results in a #GP fault, leading to a triple fault, because the GDT is erased from existance.
Edit: The BIOS doesn't do anything to the 8042 chip after reading the first reset POST initialization 0xAA byte?
Ok. So A20 is enabled when the PC AT is turned on. But which one? From what I can find IBM used the 8042 for that. But what about the fast A20(Since the PS/2)? Is fast A20 disabled by default? Or are they both enabled&disabled? They're OR'ed together, or not?
Ok. So A20 is enabled when the PC AT is turned on. But which one? From what I can find IBM used the 8042 for that. But what about the fast A20(Since the PS/2)? Is fast A20 disabled by default? Or are they both enabled&disabled? They're OR'ed together, or not?
Good question. They are ORed together on PS2, but I don't know the initial FAST A20 state. Since it boots, it's still enabled.
Is the PS/2 AT-compatible? If it is, both should be disabled on boot. Then, If it can also run 8086 wraparround hacks using the AT BIOS(both are disabled, but only the 8042 is used by the AT BIOS), that would mean it's turned off(0 in fast A20) on powerup. Anyone has an accurate emulator of an I PS/2 to run with a IBM AT BIOS?
Looking at https://github.com/OBattler/PCem-X/blob/master/PCem/mem.c shows that the keyboard is enabled by default(2) on MMU(CPU) reset and the fast version is either reset(0) every CPU reset or only during powerup(variable initialization)?
Well, the protected mode seems to work now. It gets to point 27h, after which it enters an incredibly slow DMA Refresh toggle loop(because of the JZ loop inside of a LOOP block. Currently about 0x30 per two seconds(with ~ 0x6000 left to go). So either 8086 timings(@4.77MHz) isn't enough for the BIOS, or my emulator is too slow(on my 4.0Ghz Intel i7)?
Would I need to make the 8086 timings compatible by changing the 80286 CPU timings to be accurate to actual 80286 real mode timings and clocked to a 80286 clock instead of 8086 timings@4.77MHz?
I'm just wondering: when does bit 4 of port 0x61 toggle? Every time a DMA byte is transferred on DMA0? Or every time PIT timer 1 (Port 0x41) times out? Is it the realtime status of the PIT1 1.19MHz signal?
Edit: Looking it up again reveals port 0x61 reports the status of the PIT0&2 signals on bits 5&4. Implementing this now succeeds the timing detection. The only strange thing left is that it says it's only a 100ms delay, while the actual delay takes much longer(due to the short time the bit is actually cleared). But although the delay takes a long time, it succeeds now(within a little bit of time) 😀
It now gets to checkpoint 2B.
Edit: Managed to fix IRQ bugs. It now fully supports edge-triggered (low-to-high) IRQs. The PIT0 signal is now directly passed to raise/lower irq(IR0 input) calls(which handle raising and lowering of it's signals).
Inhabiting the IRQ0 raised value of the Interrupt Request now disables the IRR value accordingly, with no more IRQs being generated until another rising IR0(IR0 isn't changed by port 0x61 anymore, only by the PIT's Timer 0 output).
It now also displays the first part (64k) of the memory test it's supposed to be doing in protected mode:)
The display now reads:
100064 KB OK 2 3010000 0000 201-Memory Error
The POST log reads:
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Code: A3 17300:00:03:55.05029: POST Code: A4 17400:00:03:55.05319: POST Code: A5 17500:00:03:55.05591: POST Code: A6 17600:00:03:55.05863: POST Code: A7 17700:00:03:55.06167: POST Code: A8 17800:00:03:55.06447: POST Code: A9 17900:00:03:55.06717: POST Code: AA 18000:00:03:55.06991: POST Code: AB 18100:00:03:55.07261: POST Code: AC 18200:00:03:55.07553: POST Code: AD 18300:00:03:55.07825: POST Code: AE 18400:00:03:55.08096: POST Code: AF 18500:00:03:55.08367: POST Code: B0 18600:00:03:55.08659: POST Code: B1 18700:00:03:55.08940: POST Code: B2 18800:00:03:55.09211: POST Code: B3 18900:00:03:55.09516: POST Code: B4 19000:00:03:55.09781: POST Code: B5 19100:00:03:56.00066: POST Code: B6 19200:00:03:56.00330: POST Code: B7 19300:00:03:56.00653: POST Code: B8 19400:00:03:56.01038: POST Code: B9 19500:00:03:56.01354: POST Code: BA 19600:00:03:56.01630: POST Code: BB 19700:00:03:56.01979: POST Code: BC 19800:00:03:56.02245: POST Code: BD 19900:00:03:56.02564: POST Code: BE 20000:00:03:56.02834: POST Code: BF 20100:00:03:56.03117: POST Code: C0 20200:00:03:56.03465: POST Code: C1 20300:00:03:56.03752: POST Code: C2 20400:00:03:56.04078: POST Code: C3 20500:00:03:56.04342: POST Code: C4 20600:00:03:56.04626: POST Code: C5 20700:00:03:56.04901: POST Code: C6 20800:00:03:56.05198: POST Code: C7 20900:00:03:56.05482: POST Code: C8 21000:00:03:56.05746: POST Code: C9 21100:00:03:56.06051: POST Code: CA 21200:00:03:56.06315: POST Code: CB 21300:00:03:56.06597: POST Code: CC 21400:00:03:56.06862: POST Code: CD 21500:00:03:56.07195: POST Code: CE 21600:00:03:56.07502: POST Code: CF 21700:00:03:56.07765: POST Code: D0 21800:00:03:56.08049: POST Code: D1 21900:00:03:56.08313: POST Code: D2 22000:00:03:56.08597: POST Code: D3 22100:00:03:56.08861: POST Code: D4 22200:00:03:56.09143: POST Code: D5 22300:00:03:56.09438: POST Code: D6 22400:00:03:56.09709: POST Code: D7 22500:00:03:57.00065: POST Code: D8 22600:00:03:57.00340: POST Code: D9 22700:00:03:57.00614: POST Code: DA 22800:00:03:57.01051: POST Code: DB 22900:00:03:57.01335: POST Code: DC 23000:00:03:57.01684: POST Code: DD 23100:00:03:57.01987: POST Code: DE 23200:00:03:57.02253: POST Code: DF 23300:00:03:57.02572: POST Code: E0 23400:00:03:57.02901: POST Code: E1 23500:00:03:57.03176: POST Code: E2 23600:00:03:57.03472: POST Code: E3 23700:00:03:57.03768: POST Code: E4 23800:00:03:57.04077: POST Code: E5 23900:00:03:57.04339: POST Code: E6 24000:00:03:57.04623: POST Code: E7 24100:00:03:57.04896: POST Code: E8 24200:00:03:57.05172: POST Code: E9 24300:00:03:57.05475: POST Code: EA 24400:00:03:57.05737: POST Code: EB 24500:00:03:57.06082: POST Code: EC 24600:00:03:57.06391: POST Code: ED 24700:00:03:57.06685: POST Code: EE 24800:00:03:57.07005: POST Code: EF 24900:00:03:58.02167: POST Code: F0 25000:00:03:58.02445: POST Code: F1 25100:00:03:58.02716: POST Code: F2 25200:00:03:58.03085: POST Code: F3 25300:00:03:58.03354: POST Code: F4 25400:00:03:58.03692: POST Code: F5 25500:00:03:58.03967: POST Code: F6 25600:00:03:58.04238: POST Code: F7 25700:00:03:58.04545: POST Code: F8 25800:00:03:58.04816: POST Code: F9 25900:00:03:58.05089: POST Code: FA 26000:00:03:58.05359: POST Code: FB 26100:00:03:58.05664: POST Code: FC 26200:00:03:58.05937: POST Code: FD 26300:00:03:58.06262: POST Code: 09 26400:00:03:65.09551: POST Code: 0A 26500:00:03:65.09578: POST Code: 0B 26600:00:03:65.09622: POST Code: 0C 26700:00:03:65.09684: POST Code: 0E 26800:00:03:65.09712: POST Code: 0F 26900:00:05:40.02817: POST Code: 32 27000:00:05:78.02603: POST Code: 11 27100:00:16:56.09135: POST Code: 12 27200:00:16:56.09454: POST Code: 13 27300:00:16:56.09480: POST Code: 14 27400:00:16:57.00731: POST Code: 15 27500:00:16:57.00908: POST Code: 16 27600:00:16:57.01005: POST Code: 17 27700:00:16:57.01137: POST Code: 18 27800:00:16:57.01147: POST Code: 19 27900:00:16:57.01200: POST Code: 81 28000:00:16:57.05840: POST Code: 85 28100:00:16:57.05848: POST Code: 1A 28200:00:16:57.05891: POST Code: 1B 28300:00:27:20.05532: POST Code: 1C 28400:00:27:20.05684: POST Code: 1D 28500:00:31:95.08104: POST Code: 1E 28600:00:31:95.08198: POST Code: 1F 28700:00:31:95.08378: POST Code: 20 28800:00:31:95.08552: POST Code: 21 28900:00:32:26.09228: POST Code: 23 29000:00:37:33.07304: POST Code: 24 29100:00:37:33.07628: POST Code: 25 29200:00:37:33.07656: POST Code: 26 29300:02:13:03.03048: F000:1A37 (E461)IN AL, 61 29400:02:13:03.03056: Registers: 29500:02:13:03.03056: AX: 1010, BX: 0000, CX: 0EAD, DX: C800 29600:02:13:03.03064: CS: F000, DS: 0040, ES: 0040, SS: 0000 29700:02:13:03.03072: SP: 03FC, BP: 0000, SI: 0AD7, DI: 0000 29800:02:13:03.03072: IP: 1A37, FLAGS: 0246 29900:02:13:03.03080: FLAGSINFO:c1P0a0ZstIdo00n0 30000:02:13:03.03088: Interrupt status: 0000000000000010 30100:02:13:03.03088: VGA@195,212(CRT:222,246) 30200:02:13:03.03096: Display=801,446 303 30400:02:13:77.06568: F000:1A39 (2410)AND AL, 10 30500:02:13:77.06576: Registers: 30600:02:13:77.06584: AX: 10B0, BX: 0000, CX: 0EAD, DX: C800 30700:02:13:77.06584: CS: F000, DS: 0040, ES: 0040, SS: 0000 30800:02:13:77.06592: SP: 03FC, BP: 0000, SI: 0AD7, DI: 0000 30900:02:13:77.06608: IP: 1A39, FLAGS: 0246 31000:02:13:77.06608: FLAGSINFO:c1P0a0ZstIdo00n0 31100:02:13:77.06816: Interrupt status: 0000000000000010 31200:02:13:77.06824: VGA@244,212(CRT:271,246) 31300:02:13:77.06832: Display=801,446 314 31500:02:14:25.06336: F000:1A3B (3AC4)CMPB AL,AH 31600:02:14:25.06352: Registers: 31700:02:14:25.06352: AX: 1010, BX: 0000, CX: 0EAD, DX: C800 31800:02:14:25.06368: CS: F000, DS: 0040, ES: 0040, SS: 0000 31900:02:14:25.06368: SP: 03FC, BP: 0000, SI: 0AD7, DI: 0000 32000:02:14:25.06368: IP: 1A3B, FLAGS: 0202 32100:02:14:25.06384: FLAGSINFO:c1p0a0zstIdo00n0 32200:02:14:25.06384: Interrupt status: 0000000000000010 32300:02:14:25.06592: VGA@264,212(CRT:291,246) 32400:02:14:25.06592: Display=801,446 325 32600:02:14:71.04992: F000:1A3D (74F8)JZ 1A37 32700:02:14:71.05008: Registers: 32800:02:14:71.05008: AX: 1010, BX: 0000, CX: 0EAD, DX: C800 32900:02:14:71.05008: CS: F000, DS: 0040, ES: 0040, SS: 0000 33000:02:14:71.05024: SP: 03FC, BP: 0000, SI: 0AD7, DI: 0000 33100:02:14:71.05024: IP: 1A3D, FLAGS: 0246 33200:02:14:71.05024: FLAGSINFO:c1P0a0ZstIdo00n0 33300:02:14:71.05264: Interrupt status: 0000000000000010 33400:02:14:71.05264: VGA@278,212(CRT:305,246) 33500:02:14:71.05264: Display=801,446 336 33700:02:16:65.09056: F000:1A41 (E2F4)LOOP 1A37 33800:02:16:65.09072: Registers: 33900:02:16:65.09072: AX: 0000, BX: 0000, CX: 0EAD, DX: C800 34000:02:16:65.09072: CS: F000, DS: 0040, ES: 0040, SS: 0000 34100:02:16:65.09088: SP: 03FC, BP: 0000, SI: 0AD7, DI: 0000 34200:02:16:65.09088: IP: 1A41, FLAGS: 0287 34300:02:16:65.09088: FLAGSINFO:C1P0a0zStIdo00n0 34400:02:16:65.09360: Interrupt status: 0000000000000010 34500:02:16:65.09376: VGA@217,281(CRT:244,315) 34600:02:16:65.09376: Display=801,446 347 34800:04:14:95.08768: POST Code: 27 34900:04:15:07.05760: POST Code: 29 35000:04:15:07.05808: POST Code: 2A 35100:04:15:07.05952: POST Code: 2B 35200:04:15:07.06048: POST Code: 2C 35300:04:15:07.06240: POST Code: 2D 35400:04:15:07.06256: POST Code: 2F 35500:04:15:07.06272: POST Code: 30 35600:04:15:07.06336: POST Code: 81 35700:04:15:08.07568: POST Code: 85 35800:04:15:08.07584: POST Code: 31 35900:04:15:10.05008: POST Code: 00
Just managed to get it working further. It now checks memory up to 256K, then gives a memory error (I see accesses to physical address A0000+)? The VGA isn't mapped at that point?
By looking at a simple log of loaded descriptors, all seems fine up until the error:
100:00:03:29.09396: POST Code: 01 200:00:03:30.00288: POST Code: 02 300:00:03:53.08812: POST Code: 03 400:00:03:53.09056: POST Code: 04 500:00:03:53.09110: POST Code: 05 600:00:03:53.09187: POST Code: 06 700:00:03:53.09917: POST Code: 07 800:00:03:54.00679: POST Code: 08 900:00:03:54.00976: POST Code: 00 1000:00:03:54.01238: POST Code: 01 1100:00:03:54.01522: POST Code: 02 1200:00:03:54.01785: POST Code: 03 1300:00:03:54.02083: POST Code: 04 1400:00:03:54.02364: POST Code: 05 1500:00:03:54.02683: POST Code: 06 1600:00:03:54.03041: POST Code: 07 1700:00:03:54.03534: POST Code: 08 1800:00:03:54.03816: POST Code: 09 1900:00:03:54.04176: POST Code: 0A 2000:00:03:54.04483: POST Code: 0B 2100:00:03:54.04803: POST Code: 0C 2200:00:03:54.05112: POST Code: 0D 2300:00:03:54.05443: POST Code: 0E 2400:00:03:55.00244: POST Code: 0F 2500:00:03:55.00594: POST Code: 10 2600:00:03:55.00870: POST Code: 11 2700:00:03:55.01145: POST Code: 12 2800:00:03:55.01438: POST Code: 13 2900:00:03:55.01707: POST Code: 14 3000:00:03:55.02015: POST Code: 15 3100:00:03:55.02279: POST Code: 16 3200:00:03:55.02603: POST Code: 17 3300:00:03:55.02888: POST Code: 18 3400:00:03:55.03151: POST Code: 19 3500:00:03:55.03460: POST Code: 1A 3600:00:03:55.03721: POST Code: 1B 3700:00:03:55.04028: POST Code: 1C 3800:00:03:55.04293: POST Code: 1D 3900:00:03:55.04580: POST Code: 1E 4000:00:03:55.04843: POST Code: 1F 4100:00:03:55.05146: POST Code: 20 4200:00:03:55.05443: POST Code: 21 4300:00:03:55.05706: POST Code: 22 4400:00:03:55.06001: POST Code: 23 4500:00:03:55.06265: POST Code: 24 4600:00:03:55.06573: POST Code: 25 4700:00:03:55.06948: POST Code: 26 4800:00:03:55.07212: POST Code: 27 4900:00:03:55.07498: POST Code: 28 5000:00:03:55.07761: POST Code: 29 5100:00:03:55.08066: POST Code: 2A 5200:00:03:55.08332: POST Code: 2B 5300:00:03:55.08653: POST Code: 2C 5400:00:03:55.08956: POST Code: 2D 5500:00:03:55.09283: POST Code: 2E 5600:00:03:55.09687: POST Code: 2F 5700:00:03:56.00050: POST Code: 30 5800:00:03:56.00328: POST Code: 31 5900:00:03:56.00615: POST Code: 32 6000:00:03:56.00921: POST Code: 33
…Show last 380 lines
6100:00:03:56.01185: POST Code: 34 6200:00:03:56.01507: POST Code: 35 6300:00:03:56.01800: POST Code: 36 6400:00:03:56.02079: POST Code: 37 6500:00:03:56.02418: POST Code: 38 6600:00:03:56.02730: POST Code: 39 6700:00:03:56.03036: POST Code: 3A 6800:00:03:56.03302: POST Code: 3B 6900:00:03:56.03594: POST Code: 3C 7000:00:03:56.03879: POST Code: 3D 7100:00:03:56.04143: POST Code: 3E 7200:00:03:56.04450: POST Code: 3F 7300:00:03:56.04713: POST Code: 40 7400:00:03:56.04999: POST Code: 41 7500:00:03:56.05263: POST Code: 42 7600:00:03:56.05601: POST Code: 43 7700:00:03:56.05908: POST Code: 44 7800:00:03:56.06233: POST Code: 45 7900:00:03:56.06622: POST Code: 46 8000:00:03:56.06914: POST Code: 47 8100:00:03:56.07185: POST Code: 48 8200:00:03:56.07478: POST Code: 49 8300:00:03:56.07747: POST Code: 4A 8400:00:03:56.08040: POST Code: 4B 8500:00:03:56.08315: POST Code: 4C 8600:00:03:56.08636: POST Code: 4D 8700:00:03:56.08968: POST Code: 4E 8800:00:03:56.09241: POST Code: 4F 8900:00:03:56.09604: POST Code: 50 9000:00:03:56.09905: POST Code: 51 9100:00:03:57.00169: POST Code: 52 9200:00:03:57.00456: POST Code: 53 9300:00:03:57.00720: POST Code: 54 9400:00:03:57.01014: POST Code: 55 9500:00:03:57.01278: POST Code: 56 9600:00:03:57.01563: POST Code: 57 9700:00:03:57.01827: POST Code: 58 9800:00:03:57.02110: POST Code: 59 9900:00:03:57.02405: POST Code: 5A 10000:00:03:57.02675: POST Code: 5B 10100:00:03:57.02987: POST Code: 5C 10200:00:03:57.03271: POST Code: 5D 10300:00:03:57.03674: POST Code: 5E 10400:00:03:57.04175: POST Code: 5F 10500:00:03:57.04685: POST Code: 60 10600:00:03:57.05192: POST Code: 61 10700:00:03:57.05697: POST Code: 62 10800:00:03:57.06198: POST Code: 63 10900:00:03:57.06713: POST Code: 64 11000:00:03:57.07213: POST Code: 65 11100:00:03:57.07727: POST Code: 66 11200:00:03:57.08228: POST Code: 67 11300:00:03:58.04430: POST Code: 68 11400:00:03:58.04815: POST Code: 69 11500:00:03:58.05141: POST Code: 6A 11600:00:03:58.05548: POST Code: 6B 11700:00:03:58.05817: POST Code: 6C 11800:00:03:58.06113: POST Code: 6D 11900:00:03:58.06409: POST Code: 6E 12000:00:03:58.06697: POST Code: 6F 12100:00:03:58.07052: POST Code: 70 12200:00:03:58.07323: POST Code: 71 12300:00:03:58.07613: POST Code: 72 12400:00:03:58.07950: POST Code: 73 12500:00:03:58.08266: POST Code: 74 12600:00:03:58.08794: POST Code: 75 12700:00:03:58.09165: POST Code: 76 12800:00:03:58.09459: POST Code: 77 12900:00:03:58.09769: POST Code: 78 13000:00:03:59.00059: POST Code: 79 13100:00:03:59.00330: POST Code: 7A 13200:00:03:59.00639: POST Code: 7B 13300:00:03:59.00929: POST Code: 7C 13400:00:03:59.01197: POST Code: 7D 13500:00:03:59.01490: POST Code: 7E 13600:00:03:59.01759: POST Code: 7F 13700:00:03:59.02048: POST Code: 80 13800:00:03:59.02318: POST Code: 81 13900:00:03:59.02607: POST Code: 82 14000:00:03:59.02895: POST Code: 83 14100:00:03:59.03163: POST Code: 84 14200:00:03:59.03454: POST Code: 85 14300:00:03:59.03723: POST Code: 86 14400:00:03:59.04012: POST Code: 87 14500:00:03:59.04282: POST Code: 88 14600:00:03:59.04573: POST Code: 89 14700:00:03:59.04843: POST Code: 8A 14800:00:03:59.05132: POST Code: 8B 14900:00:03:59.05428: POST Code: 8C 15000:00:03:59.05696: POST Code: 8D 15100:00:03:59.05984: POST Code: 8E 15200:00:03:59.06253: POST Code: 8F 15300:00:03:59.06546: POST Code: 90 15400:00:03:59.06816: POST Code: 91 15500:00:03:59.07108: POST Code: 92 15600:00:03:59.07398: POST Code: 93 15700:00:03:59.07666: POST Code: 94 15800:00:03:59.07954: POST Code: 95 15900:00:03:59.08224: POST Code: 96 16000:00:03:59.08517: POST Code: 97 16100:00:03:59.08801: POST Code: 98 16200:00:03:59.09092: POST Code: 99 16300:00:03:59.09375: POST Code: 9A 16400:00:03:59.09701: POST Code: 9B 16500:00:03:60.00011: POST Code: 9C 16600:00:03:60.00280: POST Code: 9D 16700:00:03:60.00580: POST Code: 9E 16800:00:03:60.01085: POST Code: 9F 16900:00:03:60.01520: POST Code: A0 17000:00:03:60.01891: POST Code: A1 17100:00:03:60.02167: POST Code: A2 17200:00:03:60.02446: POST Code: A3 17300:00:03:60.02765: POST Code: A4 17400:00:03:60.03058: POST Code: A5 17500:00:03:60.03420: POST Code: A6 17600:00:03:60.03907: POST Code: A7 17700:00:03:60.04397: POST Code: A8 17800:00:03:60.04902: POST Code: A9 17900:00:03:60.05558: POST Code: AA 18000:00:03:60.06133: POST Code: AB 18100:00:03:60.06942: POST Code: AC 18200:00:03:60.07399: POST Code: AD 18300:00:03:60.08090: POST Code: AE 18400:00:03:60.08556: POST Code: AF 18500:00:03:60.09030: POST Code: B0 18600:00:03:60.09558: POST Code: B1 18700:00:03:61.00038: POST Code: B2 18800:00:03:61.00530: POST Code: B3 18900:00:03:61.01038: POST Code: B4 19000:00:03:61.01390: POST Code: B5 19100:00:03:61.01669: POST Code: B6 19200:00:03:61.07196: POST Code: B7 19300:00:03:61.07484: POST Code: B8 19400:00:03:61.07761: POST Code: B9 19500:00:03:61.08052: POST Code: BA 19600:00:03:61.08328: POST Code: BB 19700:00:03:61.08699: POST Code: BC 19800:00:03:61.09006: POST Code: BD 19900:00:03:61.09481: POST Code: BE 20000:00:03:61.09803: POST Code: BF 20100:00:03:62.00119: POST Code: C0 20200:00:03:62.00419: POST Code: C1 20300:00:03:62.00687: POST Code: C2 20400:00:03:62.00981: POST Code: C3 20500:00:03:62.01253: POST Code: C4 20600:00:03:62.01549: POST Code: C5 20700:00:03:62.01829: POST Code: C6 20800:00:03:62.02115: POST Code: C7 20900:00:03:62.02405: POST Code: C8 21000:00:03:62.02692: POST Code: C9 21100:00:03:62.02999: POST Code: CA 21200:00:03:62.03271: POST Code: CB 21300:00:03:62.03565: POST Code: CC 21400:00:03:62.03835: POST Code: CD 21500:00:03:62.04135: POST Code: CE 21600:00:03:62.04429: POST Code: CF 21700:00:03:62.04699: POST Code: D0 21800:00:03:62.04998: POST Code: D1 21900:00:03:62.05269: POST Code: D2 22000:00:03:62.05565: POST Code: D3 22100:00:03:62.05833: POST Code: D4 22200:00:03:62.06128: POST Code: D5 22300:00:03:62.06424: POST Code: D6 22400:00:03:62.06694: POST Code: D7 22500:00:03:62.06987: POST Code: D8 22600:00:03:62.07257: POST Code: D9 22700:00:03:62.07552: POST Code: DA 22800:00:03:62.07821: POST Code: DB 22900:00:03:62.08125: POST Code: DC 23000:00:03:62.08413: POST Code: DD 23100:00:03:62.08696: POST Code: DE 23200:00:03:62.08990: POST Code: DF 23300:00:03:62.09260: POST Code: E0 23400:00:03:62.09558: POST Code: E1 23500:00:03:62.09917: POST Code: E2 23600:00:03:63.00191: POST Code: E3 23700:00:03:63.00484: POST Code: E4 23800:00:03:63.00753: POST Code: E5 23900:00:03:63.01059: POST Code: E6 24000:00:03:63.01330: POST Code: E7 24100:00:03:63.01624: POST Code: E8 24200:00:03:63.01931: POST Code: E9 24300:00:03:63.02203: POST Code: EA 24400:00:03:63.02494: POST Code: EB 24500:00:03:63.02783: POST Code: EC 24600:00:03:63.03071: POST Code: ED 24700:00:03:63.03351: POST Code: EE 24800:00:03:63.03627: POST Code: EF 24900:00:03:63.03910: POST Code: F0 25000:00:03:63.04185: POST Code: F1 25100:00:03:63.04470: POST Code: F2 25200:00:03:63.04750: POST Code: F3 25300:00:03:63.05045: POST Code: F4 25400:00:03:63.05334: POST Code: F5 25500:00:03:63.05624: POST Code: F6 25600:00:03:63.05958: POST Code: F7 25700:00:03:63.06243: POST Code: F8 25800:00:03:63.06539: POST Code: F9 25900:00:03:63.06866: POST Code: FA 26000:00:03:63.07345: POST Code: FB 26100:00:03:63.07764: POST Code: FC 26200:00:03:63.08189: POST Code: FD 26300:00:03:63.08707: POST Code: 09 26400:00:03:71.07096: POST Code: 0A 26500:00:03:71.07132: POST Code: 0B 26600:00:03:71.07177: POST Code: 0C 26700:00:03:71.07240: POST Code: 0E 26800:00:03:71.07267: POST Code: 0F 26900:00:05:22.07786: POST Code: 32 27000:00:05:61.01095: POST Code: 11 27100:00:16:78.08158: POST Code: 12 27200:00:16:78.08610: POST Code: 13 27300:00:16:78.08640: POST Code: 14 27400:00:16:78.09676: POST Code: 15 27500:00:16:78.09806: POST Code: 16 27600:00:16:78.09852: POST Code: 17 27700:00:16:78.09970: POST Code: 18 27800:00:16:78.09980: POST Code: 19 27900:00:16:79.00034: POST Code: 81 28000:00:16:79.04440: Loading segment #0 with base 000F0000 28100:00:16:79.04446: POST Code: 85 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31600:00:19:25.06638: Loading segment #2 with base 0000D8A0 31700:00:19:25.06720: Loading segment #2 with base 00000400 31800:00:19:25.06732: Loading segment #2 with base 0000D8A0 31900:00:19:40.02634: Loading segment #2 with base 00090000 32000:00:19:56.03978: Loading segment #2 with base 0000D8A0 32100:00:19:56.04040: POST Code: 1C 32200:00:19:56.04182: Loading segment #0 with base 000F0000 32300:00:19:56.04252: Loading segment #0 with base 000F0000 32400:00:19:56.04266: Loading segment #2 with base 00000400 32500:00:19:56.04288: Loading segment #2 with base 0000D8A0 32600:00:19:56.04300: POST Code: 1D 32700:00:19:56.04340: Loading segment #2 with base 00000400 32800:00:19:56.04352: Loading segment #2 with base 0000D8A0 32900:00:19:70.03458: Loading segment #2 with base 00100000 33000:00:19:86.08354: Loading segment #2 with base 0000D8A0 33100:00:19:86.08412: Loading segment #2 with base 00000400 33200:00:19:86.08424: Loading segment #2 with base 0000D8A0 33300:00:20:01.00992: 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35000:00:21:39.06410: Loading segment #2 with base 0000D8A0 35100:00:21:39.06528: Loading segment #2 with base 00000400 35200:00:21:39.06550: Loading segment #2 with base 0000D8A0 35300:00:21:53.09610: Loading segment #2 with base 00160000 35400:00:21:69.07938: Loading segment #2 with base 0000D8A0 35500:00:21:69.07992: Loading segment #2 with base 00000400 35600:00:21:69.08006: Loading segment #2 with base 0000D8A0 35700:00:21:84.02840: Loading segment #2 with base 00170000 35800:00:22:00.09004: Loading segment #2 with base 0000D8A0 35900:00:22:00.09060: Loading segment #2 with base 00000400 36000:00:22:00.09072: Loading segment #2 with base 0000D8A0 36100:00:22:15.02412: Loading segment #2 with base 00180000 36200:00:22:31.08104: Loading segment #2 with base 0000D8A0 36300:00:22:31.08158: Loading segment #2 with base 00000400 36400:00:22:31.08170: Loading segment #2 with base 0000D8A0 36500:00:22:46.02936: Loading segment #2 with base 00190000 36600:00:22:62.04922: Loading segment #2 with base 0000D8A0 36700:00:22:62.04976: Loading segment #2 with base 00000400 36800:00:22:62.04990: Loading segment #2 with base 0000D8A0 36900:00:22:76.05156: Loading segment #2 with base 001A0000 37000:00:22:93.03510: Loading segment #2 with base 0000D8A0 37100:00:22:93.03562: Loading segment #2 with base 00000400 37200:00:22:93.03574: Loading segment #2 with base 0000D8A0 37300:00:23:08.05542: Loading segment #2 with base 001B0000 37400:00:23:24.00596: Loading segment #2 with base 0000D8A0 37500:00:23:24.00652: Loading segment #2 with base 00000400 37600:00:23:24.00664: Loading segment #2 with base 0000D8A0 37700:00:23:39.00516: Loading segment #2 with base 001C0000 37800:00:23:55.07188: Loading segment #2 with base 0000D8A0 37900:00:23:55.07242: Loading segment #2 with base 00000400 38000:00:23:55.07254: Loading segment #2 with base 0000D8A0 38100:00:23:69.07892: Loading segment #2 with base 001D0000 38200:00:23:85.09260: Loading segment #2 with base 0000D8A0 38300:00:23:85.09314: Loading segment #2 with base 00000400 38400:00:23:85.09326: Loading segment #2 with base 0000D8A0 38500:00:24:00.04354: Loading segment #2 with base 001E0000 38600:00:24:16.06110: Loading segment #2 with base 0000D8A0 38700:00:24:16.06160: Loading segment #2 with base 00000400 38800:00:24:16.06176: Loading segment #2 with base 0000D8A0 38900:00:24:30.09910: Loading segment #2 with base 001F0000 39000:00:24:47.00874: Loading segment #2 with base 0000D8A0 39100:00:24:47.00924: POST Code: 1E 39200:00:24:47.00966: Loading segment #0 with base 000F0000 39300:00:24:47.01012: Loading segment #0 with base 000F0000 39400:00:24:47.01028: POST Code: 1F 39500:00:24:47.01212: POST Code: 20 39600:00:24:47.01450: POST Code: 21 39700:00:24:79.09186: POST Code: 23 39800:00:29:93.05178: POST Code: 24 39900:00:29:93.05572: POST Code: 25 40000:00:29:93.05604: POST Code: 26 40100:03:46:10.03408: POST Code: 27 40200:03:46:22.08656: POST Code: 29 40300:03:46:22.08704: POST Code: 2A 40400:03:46:22.08880: POST Code: 2B 40500:03:46:22.09072: POST Code: 2C 40600:03:46:22.09456: POST Code: 2D 40700:03:46:22.09488: POST Code: 2F 40800:03:46:22.09504: POST Code: 30 40900:03:46:22.09584: POST Code: 81 41000:03:46:23.07072: Loading segment #0 with base 000F0000 41100:03:46:23.07072: POST Code: 85 41200:03:46:23.07088: POST Code: 31 41300:03:46:23.07120: Loading segment #2 with base 00000400 41400:03:46:23.09008: Loading segment #0 with base 000F0000 41500:03:46:23.09088: Loading segment #0 with base 000F0000 41600:03:46:23.09248: Loading segment #0 with base 000F0000 41700:03:46:23.09360: Loading segment #0 with base 000F0000 41800:03:46:23.09488: Loading segment #0 with base 000F0000 41900:03:46:23.09744: Loading segment #2 with base 0000D8A0 42000:03:46:23.09888: Loading segment #2 with base 00010000 42100:03:48:50.02432: POST Code: 32 42200:03:49:06.03712: Loading segment #2 with base 0000D8A0 42300:03:49:06.03776: Loading segment #2 with base 00020000 42400:03:49:06.03792: POST Code: 31 42500:03:51:36.02528: POST Code: 32 42600:03:51:91.06352: Loading segment #2 with base 0000D8A0 42700:03:51:91.06448: Loading segment #2 with base 00030000 42800:03:51:91.06464: POST Code: 31 42900:03:54:13.02880: POST Code: 32 43000:03:54:69.02784: Loading segment #2 with base 0000D8A0 43100:03:54:69.02848: Loading segment #2 with base 00040000 43200:03:54:69.02864: POST Code: 31 43300:03:54:69.03264: Loading segment #2 with base 00000400 43400:03:54:69.03328: Loading segment #0 with base 000F0000 43500:03:54:69.03376: Loading segment #0 with base 000F0000 43600:03:54:69.03440: Loading segment #0 with base 000F0000 43700:03:54:69.03504: Loading segment #0 with base 000F0000 43800:03:54:69.03552: Loading segment #0 with base 000F0000 43900:03:54:71.08048: POST Code: 00
Just CS(segment #0) and DS(Segment #2) are logged here, because the test tests using it.
Edit: Just might have found the cause: The PIT was returning the wrong channel 1 line on port 0x61, causing bit 0x40 to be set (which is incorrect) with current status 2(which isn't the line at all: it's the part of the command, being used for changing PIT states(like waiting for gates to rise, lower, step, inactive counters etc.).
101664 KB OK 2 30010000 0080 203-Memory Address Error
Although the delays using the 0x61 bit 4(PIT1 output) take terribly long for some reason? Like about 1-1.5 minute for a 100 millisecond delay according to the code. Looking at what it sets up it's about 200Hz signal resulting after division(200Hz Rate Generator)? If this is used for toggling and timing, about 200 changes each second is consumed, so the 100 millisecond taking about 6000 of those changes results in a 122 seconds delay?
The reload value is set to 0x12FF, so 1.19MHz/0x12FF=~1193181/4863=245.3 timeouts per second, thus 6628*245.3=27.01 seconds delay?
1;--- WAITF --------------------------------------------------------------- 2; FIXED TIME WAIT ROUTINE HARDWARE CONTROLLED - NOT PROCESSOR) : 3; : 4; ENTRY: : 5; (CX) = COUNT OF 15.,085737 MICROSECOND INTERVALS TO WAIT : 6; MEMORY REFRESH TIMER 1 OUTPUT USED AS REFERENCE : 7; EXIT: : 8; AFTER (CX) TIME COUNT (PLUS OR MINUS 16 MICROSECONDS) : 9; (CX) = 0 : 10;------------------------------------------------------------------------- 11 12WAITF PROC NEAR ; DELAY FOR (CX)*15.085737 US 13 PUSH AX ; SAVE WORK REGISTER (AH) 14 15WAITFI: ; USE TIMER 1 OUTPUT BITS 16 IN AL,PORT_B ; READ CURRENT COUNTER OUTPUT STATUS 17 AND AL,REFRESH_BIT ; MASK FOR REFRESH DETERMINE BIT 18 CMP AL,AH ; DID IT JUST CHANGE 19 JE WAITF1 ; WAIT FOR A CHANCE IN OUTPUT LINE 20 21 MOV AH,AL ; SAVE NEW FLAG STATE 22 LOOP WAITF1 ; DECREMENT HALF CYCLES TILL COUNT END 23 24 POP AX ; RESTORE (AH) 25 RET ; RETURN (CX)= 0 26 27WAITF ENDP
The problem with this is that the timer is set to refresh too slow (instead of a count of 72 loaded(to get the correct frequency), there's a counter of 0x12FF loaded)?
Edit: Implementing the AT PIT Read Back command and seperate hi/low byte updates has no effect it seems. The impossible big value is still set?
Well, the strange thing is: I'm receiving strange command bytes:
First it sets command byte 0x54, which sets PIT 1, mode 2, LSB
Then it sets command byte 0x40, which latches PIT1(overwrite mode to latch low, high mode).
Further commands keep being command 0x40(latch low,high mode)? Or does this latch mode only affect reads from port 0x40-0x42?
Look at the out8253/in8253 commands for the I/O from the CPU and how that's handled. tickPIT handles all timing based on the 14MHz clock and realtime clock(nanoseconds passed, used for sound updates).
Does the latch modes overwrite the current lo,hi or lo-hi mode or only used temporary until it's fully processed(and discarded(not used anymore, thus reverting to the previous non-latch mode) when being fully read/written or the command register is written)? I've roughly based it on osdev documentation, but it doesn't specify where, if at all, the command register is stored and what retains when.
Last edited by superfury on 2016-09-15, 19:35. Edited 2 times in total.