In UniPCemu, I currently have some hardware sharing the same IRQs on the system. Even more so on the XT:
IRQ2 is used by the VGA(when used by software) as well as the MPU-401.
IRQ5 is used by both the UART and the Hard Disk(IDE) emulation.

Is this a problem? IRQ5 should be able to be shared, since it used an Interrupt Identification Register(which only identifies current IRQs), as well as the ATA hard disk controller.

IRQ assignments on UniPCemu:

10 PIT0
21 PS/2(AT+) or IBM compatible keyboard
32 (S)VGA vretrace(when enabled in vertical retrace register), MPU-401(XT only)
43 UART port 2&4(Unused)
54 UART port 1(XT&AT serial mouse)&3(Unused)
65 ATA(XT only), LPT3(Unused, base port 3BC), Sound Blaster
76 FDC(Floppy), LPT2(Unused, base port 278)
87 LPT1(Connected Sound Source, base port 378)
98 RTC(AT+)
109 MPU-401(AT+)
1110
1211
1312 PS/2 mouse(PS/2+)
1413
1514 ATA(AT+)
1615 ATA(AT+)

Shared IRQs are managed through up to 16 parallel IRQ lines emulated for each of the 16 IRQ lines(so IRQ5 has sublines 0, 1 and 2 used), which are emulated accordingly. It's the hardware's task to be identifyable for the software, if used(ATA, Parallel, Floppy and Sound Blaster are detectable through register bits which one raised the IRQ). The only unidentifyable one is the MPU-401(which seems to crash the Prince of Persia game when used during the opening cutscene).

Edit: Essentially, from the PIC point of view, 16 IRQ lines are mapped to 16 interrupt handlers. Each of the 16 IRQ lines is subdivided into 16 parallel lines(IRR2), which can be raised and lowered by hardware(the shared interrupts) individually. When any of the lines is raised(from a lowered status) and the IRQ isn't masked off in any way(by Interrupt Mask Register or ISR(currently running interrupts)), it triggers an interrupt on that line and tells the hardware that's connected to the parallel line it's starting the handler(prompting the connected hardware to raise any flags for the software to identify it's being raised). It uses a simple shadow register(ISR2; one per parallel IRQ line) to keep track of currently running interrupts, while a third IRR register(IRR3) is used to keep pending interrupt requests for seperate parallel IRQ lines(IR lines, which are edge-triggered).

PIC code: https://bitbucket.org/superfury/unipcemu/src/ … pic.c?at=master

Interrupts are registered using using registerIRQ, parallel lines are raised and lowered using raiseIRQ and lowerIRQ(high 4 bits are the parallel(shared subindex) line, low 4 bits are the IR line(the shared IR line, when the high 4 bits isn't 0)).