Just was messing around with the DMA timings. Then I noticed that the bus is released on S0(at CPU T4 state), which DMA takes and immediately starts processing S0 the next cycle. As far as I then saw on the DMA timings information, the HLDA is released at T4, but not taken by the DMA until T1(so 1 state later). Then I changed the CPU to release the bus at T4, setting a flag for the DMA controller to delay. Then the DMA ticks it's cycle and finds out the CPU has released the bus, taking control of the bus(So in effect, HLDA and HOLD are set and reset on a real CPU). Then the DMA controller waits for the next cycle to check again. At that cycle(the second S0 state), it finds the BUS acquired, but the flag is set. So it decreases(clears) the flag and waits another cycle. The next cycle, it finds the bus acquired and the flag cleared, does it's checks and hardware stuff and processes to the T1 state properly.
I now ran the 8088MPH demo again, saw the delorean failing when scrolling off screen halfway, saw the raster racing fail(like usually), but when it ran the credits...
The credits didn't crash, running on, playing it's music! 😁
Any idea what's the cause?
Edit: A capture of the new DMA emulation combined with 8088MPH: https://www.dropbox.com/s/2w89ztpugf6aptx/Uni … 088MPH.wav?dl=0