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First post, by superfury

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What happens when the IMR bit for an interrupt line is set and the IR line is raised? Is the corresponding IR line within the IRR register always raised, with it being checked against IMR every instruction? Or is the IR line fully ignored while IMR is set?

So what happens when IR is raised while IMR is set? Is IRR set with a pending(spurious) interrupt, which fires when IMR is cleared?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 1 of 2, by crazyc

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If an IRQ line is raised, the bit is set in the IRR whether the line is masked or not. The IRQ will then fire when unmasked if the line is still high. If the line is lowered before unmasking the IRR bit will be cleared and no IRQ will fire. The only time you get a spurious IRQ is if the line is lowered after the CPU INT line is raised but before the INTA cycle but before the vector is returned from the PIC.

Reply 2 of 2, by superfury

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I've modified the PIC emulation accordingly(although still keeping the multiple IR lines per line combination in UniPCemu, allowing sharing of IRQs between devices(as long as they can be detected and used properly and not at the same time) using parallel IR lines on the same IR input). The AT BIOS now boots properly past the PIT checks again(previously it gave an system board error at that point with the last PIC improvements(which fixed the Windows 3.0 keyboard during it's setup process).

https://bitbucket.org/superfury/unipcemu/src/ … pic.c?at=master

Although parallel IR lines don't exist on a real PC, it's a little hack to allow multiple devices to use the IR lines in a cycle-compatible way(afaik this is only done in UniPCemu).

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io