f000:0000eeca 8A 27 mov ah,byte ds:[bx] Physical(r):000FEED4=D0(Ð); Paged(r):000FEED4=D0(Ð); Physical(r):000FEED5=E0(à); Paged(r):000FEED5=E0(à)
Registers:
EAX: 00000101 EBX: 00000090 ECX: 00002300 EDX: 000003f7
ESP: 00007bac EBP: 00007bb2 ESI: 00007c2b EDI: 0000052b
CS: f000 DS: 0040 ES: 0000 FS: 0000 GS: 0308 SS: 0000 TR: 0000 LDTR: 0000
EIP: 0000eeca EFLAGS: 00000206
CR0: 0000fff8 CR1: 00000000 CR2: 00000000 CR3: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: 00000000 DR7: 00000000
GDTR: 0000000f07300047 IDTR: 000000000000ffff
FLAGSINFO: 00000000000000vr0n00odItsz0a0P1c
RAM(r):00007BB7=01(); Physical(r):00007BB7=01(); Paged(r):00007BB7=01()
Physical(r):000FEED6=8A(Š); Paged(r):000FEED6=8A(Š); Physical(r):000FEED7=4F(O); Paged(r):000FEED7=4F(O)
f000:0000eecc 8A 46 05 mov al,byte ss:[bp+05] Physical(r):000FEED8=04(); Paged(r):000FEED8=04(); Physical(r):000FEED9=32(2); Paged(r):000FEED9=32(2)
Registers:
EAX: 00007401 EBX: 00000090 ECX: 00002300 EDX: 000003f7
ESP: 00007bac EBP: 00007bb2 ESI: 00007c2b EDI: 0000052b
CS: f000 DS: 0040 ES: 0000 FS: 0000 GS: 0308 SS: 0000 TR: 0000 LDTR: 0000
EIP: 0000eecc EFLAGS: 00000206
CR0: 0000fff8 CR1: 00000000 CR2: 00000000 CR3: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: 00000000 DR7: 00000000
GDTR: 0000000f07300047 IDTR: 000000000000ffff
FLAGSINFO: 00000000000000vr0n00odItsz0a0P1c
f000:0000eecf F6 C4 20 test ah,20 Physical(r):000FEEDA=E4(ä); Paged(r):000FEEDA=E4(ä); Physical(r):000FEEDB=3A(:); Paged(r):000FEEDB=3A(:)
Registers:
EAX: 00007401 EBX: 00000090 ECX: 00002300 EDX: 000003f7
ESP: 00007bac EBP: 00007bb2 ESI: 00007c2b EDI: 0000052b
CS: f000 DS: 0040 ES: 0000 FS: 0000 GS: 0308 SS: 0000 TR: 0000 LDTR: 0000
EIP: 0000eecf EFLAGS: 00000206
CR0: 0000fff8 CR1: 00000000 CR2: 00000000 CR3: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: 00000000 DR7: 00000000
GDTR: 0000000f07300047 IDTR: 000000000000ffff
FLAGSINFO: 00000000000000vr0n00odItsz0a0P1c
Physical(r):000FEEDC=C1(Á); Paged(r):000FEEDC=C1(Á); Physical(r):000FEEDD=74(t); Paged(r):000FEEDD=74(t)
Physical(r):000FEEDE=5F(_); Paged(r):000FEEDE=5F(_); Physical(r):000FEEDF=88(ˆ); Paged(r):000FEEDF=88(ˆ)
f000:0000eed2 74 02 je 0000eed6
Registers:
EAX: 00007401 EBX: 00000090 ECX: 00002300 EDX: 000003f7
ESP: 00007bac EBP: 00007bb2 ESI: 00007c2b EDI: 0000052b
CS: f000 DS: 0040 ES: 0000 FS: 0000 GS: 0308 SS: 0000 TR: 0000 LDTR: 0000
EIP: 0000eed2 EFLAGS: 00000202
CR0: 0000fff8 CR1: 00000000 CR2: 00000000 CR3: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: 00000000 DR7: 00000000
GDTR: 0000000f07300047 IDTR: 000000000000ffff
FLAGSINFO: 00000000000000vr0n00odItsz0a0p1c
Physical(r):000FEEE0=47(G); Paged(r):000FEEE0=47(G); Physical(r):000FEEE1=04(); Paged(r):000FEEE1=04()
f000:0000eed4 D0 E0 shl al,1 Physical(r):000FEEE2=53(S); Paged(r):000FEEE2=53(S); Physical(r):000FEEE3=BB(»); Paged(r):000FEEE3=BB(»)
Registers:
EAX: 00007401 EBX: 00000090 ECX: 00002300 EDX: 000003f7
ESP: 00007bac EBP: 00007bb2 ESI: 00007c2b EDI: 0000052b
CS: f000 DS: 0040 ES: 0000 FS: 0000 GS: 0308 SS: 0000 TR: 0000 LDTR: 0000
EIP: 0000eed4 EFLAGS: 00000202
CR0: 0000fff8 CR1: 00000000 CR2: 00000000 CR3: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: 00000000 DR7: 00000000
GDTR: 0000000f07300047 IDTR: 000000000000ffff
FLAGSINFO: 00000000000000vr0n00odItsz0a0p1c
RAM(r):00000494=00( ); Physical(r):00000494=00( ); Paged(r):00000494=00( )
Physical(r):000FEEE4=04(); Paged(r):000FEEE4=04(); Physical(r):000FEEE5=00( ); Paged(r):000FEEE5=00( )
f000:0000eed6 8A 4F 04 mov cl,byte ds:[bx+04]
Registers:
EAX: 00007402 EBX: 00000090 ECX: 00002300 EDX: 000003f7
ESP: 00007bac EBP: 00007bb2 ESI: 00007c2b EDI: 0000052b
CS: f000 DS: 0040 ES: 0000 FS: 0000 GS: 0308 SS: 0000 TR: 0000 LDTR: 0000
EIP: 0000eed6 EFLAGS: 00000212
CR0: 0000fff8 CR1: 00000000 CR2: 00000000 CR3: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: 00000000 DR7: 00000000
GDTR: 0000000f07300047 IDTR: 000000000000ffff
FLAGSINFO: 00000000000000vr0n00odItsz0A0p1c
CALLER_AL equ 0x00 ; [BP+0x00] = AL SECTORS TO READ
CALLER_AH equ 0x01 ; [BP+0x01] = AH FUNCTION NUMBER
CALLER_BL equ 0x02 ; [BP+0x02] = BL LOW PART OF DESTINATION OFFSET
CALLER_BH equ 0x03 ; [BP+0x03] = BH HIGH PART OF DESTINATION OFFSET
CALLER_CL equ 0x04 ; [BP+0x04] = CL SECTOR NUMBER
CALLER_CH equ 0x05 ; [BP+0x05] = CH TRACK SELECTED
CALLER_DL equ 0x06 ; [BP+0x06] = DL DRIVE TO USE
CALLER_DH equ 0x07 ; [BP+0x07] = DH HEAD
CALLER_SI equ 0x08 ; [BP+0x08] = SI
CALLER_DI equ 0x0A ; [BP+0x0A] = DI
CALLER_ES equ 0x0C ; [BP+0x0C] = ES DESTINATION SEGMENT
CALLER_DS equ 0x0E ; [BP+0x0E] = DS
CALLER_BP equ 0x10 ; [BP+0x10] = BP
CALLER_IP equ 0x12 ; [BP+0x12] = IP
CALLER_CS equ 0x14 ; [BP+0x14] = CS
CALLER_FLAGS equ 0x16 ; [BP+0x16] = FLAGS
ecc0: call 8fa4: Loads 40:8F(Combination hard/floppy disk card when bit 0 set)
x9190: Load media state address in BX based on [BP+06]. This results in [40:90] to be loaded for drive A(bit 0-2=media state, 4=drive established, 5=double step drive, 6-7=BPS rate(0=500k,1=300k,2=250k,3=reserved)).
xecf0: Start of the FDC operation
xca4f: Setup DMA for the transfer of data
:note opcode 86 has it's parameters reversed(two registers being switched around)? This has now been fixed(still reversed in the current log).
xc956: Enable the drive motors as required(and delay when started).
F000:0000B544 Reads the CMOS register AL into AL.
The CMOS register that's read in the relevant block is register E of the CMOS(which is set to 0x44, being two 1.44MB floppy drives).
It tests bit 7(in this case, the second floppy drive's third bit, which is set), then jumps to the code that sets the invalid 0x61 value because the bit is set(the 0x40 bit in the floppy configuration byte in the CMOS RAM)?
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