dma allows to transfer data without occupying the cpu so much; ins and outs are always done by the cpu to my knowledge

That's not what I mean. Does the CPU use an internal register to store the data for/from RAM, or does it exploit the data bus retaining the value by performing a read/write at the same time like DMA does? So write to memory at the same clocks while the hardware supplies tje data lines the very same clocks?

E.g. assert both IOW and MEMR or IOR and MEMW at the same time(performing a read directly into RAM without buffer or write from RAM directly), in just a few cycles(like DMA does)? Does it use internal buffers to store the data, or does it exploit the data bus like DMA does?

So, from https://docs.freebsd.org/doc/2.2.6-RELEASE/us … andbook293.html :

The floppy disk controller is now responsible for placing the byte to be transferred on the bus Data lines. Unless the floppy controller needs more time to get the data byte on the bus (and if the peripheral does need more time it alerts the DMA via the READY signal), the DMA will wait one DMA clock, and then de-assert the -MEMW and -IOR signals so that the memory will latch and store the byte that was on the bus, and the FDC will know that the byte has been transferred.

Simply let the hardware fill the data bus and the other side read it, like DMA does? Thus no CPU buffers?

Edit: Or is this impossible due to only having one address bus for both IO and MEM? DMA only needs one(the device being addressed using DACK instead)?

The way to think about it is that DMAs transfer between memory and some other device, without involving the CPU (other than blocking it from the bus for the duration of the transfer). Port IOs (IN(S)/OUT(S)) transfer between the CPU and some other device, without involving memory. So they're totally different things, comparable only in their purpose (either could be used to transfer between memory and an IO device) and not in implementation. From the point of view of the CPU, a port IO transfer is essentially the same as a memory transfer (just one bit is different, the bit that tells the motherboard whether to use the memory address space or the port IO address space).

A DMA does not normally involve a read cycle followed by a separate write cycle - it's a single transfer, which both the memory subsystem and the device in question are paying attention to (so there is no port IO address involved in a DMA transfer). The DMA controller has memory-to-memory copies as a feature, but it's not very useful in the PC architecture since one of the required channels is in use for DRAM refresh and the two required channels share a page register so you can only transfer with in a single 64kB page.

superfury wrote:

That's not what I mean. Does the CPU use an internal register to store the data for/from RAM, or does it exploit the data bus retaining the value by performing a read/write at the same time like DMA does? So write to memory at the same clocks while the hardware supplies tje data lines the very same clocks?

E.g. assert both IOW and MEMR or IOR and MEMW at the same time(performing a read directly into RAM without buffer or write from RAM directly), in just a few cycles(like DMA does)? Does it use internal buffers to store the data, or does it exploit the data bus like DMA does?

The CPU doesn't have IOW/MEMR/IOR/MEMW lines, it has a line for "read or write" and a line for "port IO or memory address space". Even if it did, a CPU transfer can't be between both an IO port and a memory address at the same time because there's only one address bus, so there'd be no way for the CPU to tell the device in question that it's the one involved in the transfer. It couldn't be a port address (because that uses the same lines as the memory address) and it couldn't be a DMA channel number (because that's not a concept that the CPU is aware of). So yes: there is an internal CPU register involved in the INS and OUTS instructions (probably the same one involved in MOVS).