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First post, by superfury

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What TLB lookups does a 80386 perform before giving up and traversing the page tables in RAM?

In other words, what's required for a TLB hit(validated non-faulting and non-pagetabletraversing) to succeed for reads and writes respectively?

I'd assume writes requiring to be dirty and writable in the TLB cache(nonwritable is invalid and nondirty requires traversing the PDE/PTE entries and updating the dirty bit), otherwise traversing the page tables?

But what happens during a kernel access to user memory? Does it use the user-marked TLB entries, or does it traverse the page tables(probably not faulting) and load it as a non-user TLB(U=0 in the TLB)?

Currently UniPCemu saves entries loaded and non-faulted into the TLB based on page number and present, with W=writable, P=1, U=user mode access,D=current D-bit of PTE. Writes require lookup with W=1,U=user mode access,P=1,D=1. Reads require only P=1,U=user mode access(any value of W and D).

Is that correct behaviour?

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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 1 of 1, by superfury

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Just found this: https://www.google.nl/url?sa=t&source=web&rct … b39kF-bc1kVhl8o

Figure 19.1 shows a TLB flow algorithm. Is that what x86 does as well(the way it handles access rights(page u/s, r/w and dirty bits)?

Edit: The strange thing with that is that the 80386 TR(test register)-based lookups include said access/protection bits in the tag register, not in the content register? So that would imply the four access bits are in the tag, and the value only contains the physical address? Thus requiring multiple TLB lookups for said combinations of valid read accesses being looked up(all combinations of W/D/U to be applied)? What about the U-lookup bit during kernel access to user memory pages that's cached for user or kernel in the TLB?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io