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x86 supervisor level vs paging?

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First post, by superfury

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What happens in Supervisor mode when the kernel tries to write to a read-only user page(lower 3 bits of the PDE and PTE are set to 5)? Does the write access succeed(happens according to test386.asm's tables and test routines)? So the CPL(which is zeroed) has direct effect on this(besides the tables mentioned in the CPU documentation clearly resulting in "User R", thus meaning a read-only user privilege page)?

The 80386 programmer's reference manual does state:

6.4.1.2 Type Checking
At the level of page addressing, two types are defined:
Read-only access (R/W=0)
Read/write access (R/W=1)
When the processor is executing at supervisor level, all pages are both readable and writable. When the processor is executing at user level, only pages that belong to user level and are marked for read/write access are writable; pages that belong to supervisor level are neither readable nor writable from user level.

So CPL0 ignores the R/W bits in the PDE and PTE? Also, the TLB is written as if the PDE and PTE have combined write access(required for the kernel to even address said data), forcing it to 1 instead of the PDE/PTE combined write rights(1 for writable, 0 for read-only).

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 2 of 2, by superfury

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Didn´t implement that yet. I've now added(in the latest commit) the writes to user pages in kernel mode(instead of just 'assuming' the RW to be 1 for user pages when CPL!=3(running in Kernel mode)) the user pages to fault when in kernel mode and on a 80486+ the WP bit is set in CR0.

I assume the 'kernel' (PDE.US/PTE.US either or both being 0) pages are still writable always, even in kernel mode(CPL<3) with WP set(RW in the PDE/PTE is still ignored assume to be '1'(effectively))?

Thinking about it, does WP have effect on the CPL 0 fetches/writes to the descriptor tables? Those are usually executed as CPL 0 according to the documentation, does WP have effect on those as well(I'd assume they do, with my current implementation they do)? So WP=1 and read-only kernel page still doesn't fault if it's a kernel page, but it does fault if it's a user page with RW=0, WP=1 and CPL0 for the descriptor table writeback? So COW(Copy on Write) does still WORK(or crash probably) with GDT/IDT/LDT entries?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

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