x86 nested interrupt fault timing?

Emulation of old PCs, PC hardware, or PC peripherals.

x86 nested interrupt fault timing?

Postby superfury » 2019-2-10 @ 11:16

How is interrupt timing applied when interrupts themselves fault? The documentation says stuff like to lower privilege level, to same privilege level, VM86 to PL0 etc..

What timing is applied when interrupt handling(before completing a full interrupt(reaching the CS:EIP of the destination code after a possible stack switch)) is aborted in the middle(e.g. due to a page fault on the IDT or GDT, invalid GDT descriptor, DPL violations of the IDT/GDT)? I assume the final interrupt timing is applied as usual. But what about the previous interrupts that failed on a fault(page, general protection or stack fault)? What interrupt timing is applied for those?

I currently have modified it to apply it depending on different privilege levels at different points. While faulting fetching the IDT descriptor, different level if CPL<>0, otherwise same level. IDT DPL/Type/Present checks apply RPL(IDT.selector)==CPL for said condition(same level(equal) vs different level). Then while loading the CS descriptor, the same. After loading the CS descriptor, the condition of same level is CPL==DPL(new CS descriptor). Then determining VM to PL0, the same(not applying V86 to PL0 yet), otherwise unmodified. After successful interrupt and finished interrupt, CPL==oldCPL for same level.

All those determine same-level interrupt vs different level interrupt(assuming no task gate, which uses it's own timings AFTER determining it's a task gate and the present IDT check is finished), but before the task gate is examined, after loading it's descriptor and not faulting.

Is that correct behaviour?
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