VOGONS


First post, by superfury

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Looking at the 80386 instruction set again, CR0 can't be modified from Virtual 8086 mode(throwing #GP(0)):
https://pdos.csail.mit.edu/6.828/2005/reading … /i386/MOVRS.htm

But looking at LMSW reveals something odd:
https://pdos.csail.mit.edu/6.828/2005/readings/i386/LMSW.htm

The Virtual 8086 column clearly states that it's the same exceptions as in real mode.
So, in other words, you can modify bits 1-15 of CR0 from Virtual 8086 mode? So that exposes all FPU related functionality from CR0?

The only good thing about that is that you cannot clear the PE bit(bit 0) in CR0.
But you CAN modify bits 1-4, which may or may not be essential, according to that documentation from Intel.

Oddly enough, https://www.felixcloutier.com/x86/lmsw does state it throws #GP(0) in said mode?

So does it or does it not throw #GP(0) in V86 mode?

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