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First post, by superfury

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I know some code can disable A20 and triple fault/hardware CPU reset(using e.g. the 8042 Controller or the system board port B) etc. to generate a CPU reset and catch the CPU information stored in EDX::EAX(model number etc.) after reset using a #UD handler installed in memory.

Isn't A20 supposed to be reset when the CPU is reset using port B, 8042 Controller and Triple fault? I've built my emulator for any CPU reset(triggered by any of those) to enable the A20 line again(and disable any of those alternative masking the port to wrap from 1-2 (/3-4, 5-6MB etc., depending on the emulated motherboard(Compaq or not)).

Is that correct behaviour on a Compaq Deskpro 386(and IBM AT)?

Edit: What about the shutdown cycle caused by a triple fault? Will it always enable the A20 gate(from both port B and 8042)?
Edit: See also: http://www.rcollins.org/Productivity/A20Reset.html

Last edited by superfury on 2019-03-06, 20:47. Edited 1 time in total.

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Reply 1 of 3, by superfury

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So, in short, what happens when a triple fault occurs and A20 is gated off(forced to 0), so triggered by e.g. LIDT a limit of 0 in real mode and then raising an interrupt? Is A20 automatically enabled when the motherboard receives a shutdown cycle on it's bus?
So (in real mode):

lidt cs:[invidtr]
int 0 ;Any will do
invidtr: dw 0 ;Limit less than 3
dd 0 ;Not used

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Reply 3 of 3, by superfury

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So, a normal CPU reset(using the 8042 output port and system control port A(port 92h)) will leave the A20 line alone(other than their own effects, being written to setting said gate appropriately), but a shutdown signal on yhe bus(by the CPU) will always set A20 to be enabled?

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