What does the IDT's Access Rights' Size-bit control(bit 3 of the Access Rights for Interrupt and Trap gates)? All I can find are descriptions saying 16-bit for 0 and 32-bit for 1. But there's no explanation I can find ANYWHERE what this bitness applies to? It can't be stack size, as that's done by the stack segment's B-bit. Code size is done by the D-bit inside the CS descriptor that's loaded. Then EIP vs IP(discarding bits 16-31 of the descriptor at bytes 6-7 when loading into EIP)? It looks like a bit toggle for the gates, since it applies the same way for all of them(except task gates, which have no 32-bit version, thus invalid(done by task switching itself in '16-bit mode'(or 'no mode', as it doesn't apply for tasks through hardware task switching, entirely TSS descriptor dependant)))?

Does it directly affect the entries pushed on the stack(effectively being the 'Operand size' for stack pushes during interrupts(word vs dword pushes as well as decreasing (E)SP by 2 or 4) depending on that bit)? And that applies to all different kinds of protected mode interrupts(V86 to PL0 stack pushes as well)?

Is there other things affected by this bit? Anyone?
Edit: So it selects between these two? https://images.slideplayer.com/15/4826083/slides/slide_6.jpg
Although SP vs ESP isn't determined by said bit(by the SS PL0 descriptor's (D/)B(ig)-bit instead).
Weirdly enough, nowhere else it explains those images, not even in Intel's own 80386/80486 programmer's reference manuals! That's kind of strange, as it only talks about the 32-bit one(even worse, the 80386 programmer's reference manual doesn't even mention the 16-bit ones in it's chapters regarding interrupts! ).