One little question: From when to when is the lock signal active? As I've currently implemented it, it starts during the first memory access by an instruction with a LOCK(0xF0) prefix(when accessing the first byte in memory, by the BIU, of the byte/word/dword value to be read/written(it doesn't differentiate between those, either one raises the LOCK# signal)). It ends(lowers the LOCK# signal) when the instruction has completed it's opcode handler and indicates it's finished(although this includes interrupts that fault during that time, which currently aren't handled through the BIU, but directly translate and access memory, bypassing the BIU timing handling). The instruction timing might not be finished yet, however. If the final instruction step completes from the current opcode handler and it returns some leftover timing for the instruction to the BIU to tick, said remaining ticks are made with the LOCK# signal disabled(as, to the EU, the instruction is finished(except still got some leftover time to tick)).
One little question then, about HLDA. Will the CPU(Actually the BIU?) assert HLDA in the middle of executing an instruction? So if a CMPXCHG instruction is running, or an INC/DEC etc.? The algorithm my BIU currently uses to do that(releasing the bus in my emulator), is just release the bus whenever it stalls the BIU(due to an instruction(e.g. jump) requesting it), T1 with nothing to prefetch(buffer is full) or transferring state from T4(80(1)8X)/T2(80286+) to T1.